<manifestation xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:tucdl="http://purl.tuc.gr/dl/dias/schemas/aip/tucdl/" xmlns="http://purl.tuc.gr/dl/dias/schemas/aip/tucdl/" keyIdentifier="http://purl.tuc.gr/dl/dias/20020614-8894-4610-8D0E-C6C5E5F64E63" xsi:schemaLocation="http://purl.tuc.gr/dl/dias/schemas/aip/tucdl/ http://purl.tuc.gr/dl/dias/schemas/aip/tucdl"><titleOfTheManifestation>Sidiropoulos_Stefanos_Dip_2017.pdf</titleOfTheManifestation><isEmbodimentOf entityType="Expression"><uri>http://purl.tuc.gr/dl/dias/C1E23450-7859-4326-93EA-1567F85D253E</uri><title xml:lang="en">Επιτάχυνση διανυσματικού πολλαπλασιασμού πινάκων με χρήση FPGA και HLS</title></isEmbodimentOf><accessRestrictionOnTheManifestation>free</accessRestrictionOnTheManifestation><dateOfPublicationDistribution>2017-02-08</dateOfPublicationDistribution><formOfCarrier>application/pdf</formOfCarrier><extentOfTheCarrier xml:lang="en">1.8 MB</extentOfTheCarrier></manifestation>