<efrbr:recordSet xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:efrbr="http://vfrbr.info/efrbr/1.1" xmlns:efrbr-work="http://vfrbr.info/efrbr/1.1/work" xmlns:efrbr-expression="http://vfrbr.info/efrbr/1.1/expression" xmlns:efrbr-manifestation="http://vfrbr.info/efrbr/1.1/manifestation" xmlns:efrbr-person="http://vfrbr.info/efrbr/1.1/person" xmlns:efrbr-corporateBody="http://vfrbr.info/efrbr/1.1/corporateBody" xmlns:efrbr-concept="http://vfrbr.info/efrbr/1.1/concept" xmlns:efrbr-structure="http://vfrbr.info/efrbr/1.1/structure" xmlns:efrbr-responsible="http://vfrbr.info/efrbr/1.1/responsible" xmlns:efrbr-subject="http://vfrbr.info/efrbr/1.1/subject" xmlns:efrbr-other="http://vfrbr.info/efrbr/1.1/other" xsi:schemaLocation="http://vfrbr.info/efrbr/1.1 http://vfrbr.info/schemas/1.1/efrbr.xsd"><efrbr:entities><efrbr-work:work identifier="http://purl.tuc.gr/dl/dias/0FD55AC1-C9E0-4548-AC2A-7DBE50C763CC"><efrbr-work:titleOfTheWork>Exploring modern FPGA platforms for faster phylogeny reconstruction with RAxML</efrbr-work:titleOfTheWork></efrbr-work:work><efrbr-expression:expression identifier="http://purl.tuc.gr/dl/dias/0FD55AC1-C9E0-4548-AC2A-7DBE50C763CC"><efrbr-expression:titleOfTheExpression>Exploring modern FPGA platforms for faster phylogeny reconstruction with RAxML</efrbr-expression:titleOfTheExpression><efrbr-expression:formOfExpression vocabulary="DIAS:TYPES">
            Δημοσίευση σε Συνέδριο
            Conference Publication
         </efrbr-expression:formOfExpression><efrbr-expression:dateOfExpression type="issued">2022-01-07</efrbr-expression:dateOfExpression><efrbr-expression:dateOfExpression type="published">2020</efrbr-expression:dateOfExpression><efrbr-expression:languageOfExpression vocabulary="iso639-1">en</efrbr-expression:languageOfExpression><efrbr-expression:summarizationOfContent>The Phylogenetic Likelihood Function (PLF) is one of the cornerstone functions in most phylogenetic inference tools; its execution represents the majority of time required to complete an analysis. This work proposes the acceleration of this function using reconfigurable hardware accelerators, focusing on system-on-chips that integrate Field Programmable Gate Array (FPGA) resources as well as traditional High Performance Computing (HPC) systems that use FPGA-based accelerator cards. Taking into account the specific properties of each platform in order to exploit their processing capabilities, the proposed solutions provide significant performance gains. The measured acceleration of PLF function is up to 8x while the overall time to complete a phylogenetic analysis using the popular RAxML software can be reduced up to 3.2 times (with respect to a pure software implementation on a high-end server processor). Compared to other similar solutions proposed in literature, our systems perform up to 65% faster.</efrbr-expression:summarizationOfContent><efrbr-expression:useRestrictionsOnTheExpression type="creative-commons">http://creativecommons.org/licenses/by/4.0/</efrbr-expression:useRestrictionsOnTheExpression><efrbr-expression:note type="page range">97-104</efrbr-expression:note><efrbr-expression:note type="conference name">2020 IEEE 20th International Conference on Bioinformatics and Bioengineering</efrbr-expression:note><efrbr-expression:note type="proceedings title">Proceedings - IEEE 20th International Conference on Bioinformatics and Bioengineering</efrbr-expression:note></efrbr-expression:expression><efrbr-person:person identifier="http://users.isc.tuc.gr/~pmalakonakis"><efrbr-person:nameOfPerson vocabulary="TUC:LDAP">
            Malakonakis Pavlos
            Μαλακωνακης Παυλος
         </efrbr-person:nameOfPerson></efrbr-person:person><efrbr-person:person identifier="http://users.isc.tuc.gr/~abrokalakis1"><efrbr-person:nameOfPerson vocabulary="TUC:LDAP">
            Brokalakis Andreas
            Μπροκαλακης Ανδρεας
         </efrbr-person:nameOfPerson></efrbr-person:person><efrbr-person:person identifier="http://users.isc.tuc.gr/~nalachiotis1"><efrbr-person:nameOfPerson vocabulary="TUC:LDAP">
            Alachiotis Nikolaos
            Αλαχιωτης Νικολαος
         </efrbr-person:nameOfPerson></efrbr-person:person><efrbr-person:person identifier="http://users.isc.tuc.gr/~esotiriadis"><efrbr-person:nameOfPerson vocabulary="TUC:LDAP">
            Sotiriadis Evripidis
            Σωτηριαδης Ευριπιδης
         </efrbr-person:nameOfPerson></efrbr-person:person><efrbr-person:person identifier="http://users.isc.tuc.gr/~adollas"><efrbr-person:nameOfPerson vocabulary="TUC:LDAP">
            Dollas Apostolos
            Δολλας Αποστολος
         </efrbr-person:nameOfPerson></efrbr-person:person><efrbr-corporateBody:corporateBody identifier="https://v2.sherpa.ac.uk/id/publisher/38"><efrbr-corporateBody:nameOfTheCorporateBody vocabulary="S/R:PUBLISHERS">
            Institute of Electrical and Electronics Engineers
         </efrbr-corporateBody:nameOfTheCorporateBody></efrbr-corporateBody:corporateBody><efrbr-concept:concept identifier="E25572EB-46F1-4F99-9F16-8A00C4A91E7C"><efrbr-concept:termForTheConcept>
            Phylogenetic inference
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="57631A63-AA01-46D9-8514-D5B9DF3E2929"><efrbr-concept:termForTheConcept>
            Phylogenetic tree
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="11BCB2F2-7BEE-4740-9F4A-3F6DE69E3E64"><efrbr-concept:termForTheConcept>
            RAxML (Randomized Axelerated Maximum Likelihood)
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="8B22E081-414A-4DB8-9265-7CF1FD9AE255"><efrbr-concept:termForTheConcept>
            PLF (Phylogenetic Likelihood Function) 
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="BE2279E1-13C9-491F-AD4E-6240B301E3AE"><efrbr-concept:termForTheConcept>
            Phylogenetic likelihood
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="2A84D151-1BE1-492D-A7AB-0E546DAD4F52"><efrbr-concept:termForTheConcept>
            FPGA (Field Programmable Gate Array)
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="7259D858-5631-4BDF-B3E7-D1A64C5220EC"><efrbr-concept:termForTheConcept>
            Reconfigurable hardware
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="4B1785E9-4F93-44AF-91F0-6B10AF806C8E"><efrbr-concept:termForTheConcept>
            Amazon AWS F1
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