Compact modeling of SIC and gan junction FETS at high temperatureCompact modeling of SIC and gan junction FETS at high temperature Peer-Reviewed Journal Publication Δημοσίευση σε Περιοδικό με Κριτές 2020-10-272019enHigh temperatures and other harsh environments are domains of predilection for Junction FETs, particularly when wide band-gap semiconductors such as SiC or GaN are used. The present work describes the new compact model of double-gate (DG) JFETs which is compared to TCAD simulations of SiC and GaN JFETs over a wide temperature range up to 500ºC. The compact model is shown to be predictive of device behavior, for static (current-voltage) as well as dynamic (capacitance-voltage) behavior of long-channel DG JFETs.http://creativecommons.org/licenses/by/4.0/Materials Science Forum963683-687 Makris Nikolaos Μακρης Νικολαος Zekentes, Konstantinos Bucher Matthias Bucher Matthias Trans Tech Publications Capacitances Compact model Gallium Nitride High temperature JFET Junction FET On resistance Parameter extraction Silicon Carbide Wide-bandgap