<efrbr:recordSet xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:efrbr="http://vfrbr.info/efrbr/1.1" xmlns:efrbr-work="http://vfrbr.info/efrbr/1.1/work" xmlns:efrbr-expression="http://vfrbr.info/efrbr/1.1/expression" xmlns:efrbr-manifestation="http://vfrbr.info/efrbr/1.1/manifestation" xmlns:efrbr-person="http://vfrbr.info/efrbr/1.1/person" xmlns:efrbr-corporateBody="http://vfrbr.info/efrbr/1.1/corporateBody" xmlns:efrbr-concept="http://vfrbr.info/efrbr/1.1/concept" xmlns:efrbr-structure="http://vfrbr.info/efrbr/1.1/structure" xmlns:efrbr-responsible="http://vfrbr.info/efrbr/1.1/responsible" xmlns:efrbr-subject="http://vfrbr.info/efrbr/1.1/subject" xmlns:efrbr-other="http://vfrbr.info/efrbr/1.1/other" xsi:schemaLocation="http://vfrbr.info/efrbr/1.1 http://vfrbr.info/schemas/1.1/efrbr.xsd"><efrbr:entities><efrbr-work:work identifier="http://purl.tuc.gr/dl/dias/6E4A6214-112B-4C86-864B-C64564839E78"><efrbr-work:titleOfTheWork>An FPGA-based architecture to simulate cellular automata with large neighborhoods in real time</efrbr-work:titleOfTheWork></efrbr-work:work><efrbr-expression:expression identifier="http://purl.tuc.gr/dl/dias/6E4A6214-112B-4C86-864B-C64564839E78"><efrbr-expression:titleOfTheExpression>An FPGA-based architecture to simulate cellular automata with large neighborhoods in real time</efrbr-expression:titleOfTheExpression><efrbr-expression:formOfExpression vocabulary="DIAS:TYPES">
            Πλήρης Δημοσίευση σε Συνέδριο
            Conference Full Paper
         </efrbr-expression:formOfExpression><efrbr-expression:dateOfExpression type="issued">2020-04-23</efrbr-expression:dateOfExpression><efrbr-expression:dateOfExpression type="published">2019</efrbr-expression:dateOfExpression><efrbr-expression:languageOfExpression vocabulary="iso639-1">en</efrbr-expression:languageOfExpression><efrbr-expression:summarizationOfContent>In this paper we present a reconfigurable logic-based parallel architecture for the computation of 29X29 large-neighborhood cellular automata at 60 frames-per-second (FPS) real time update rate, using a small FPGA. The computation for each one of the n^2 elements of a two-dimensional input is O(κ2), where k is the size of the neighborhood in each dimension. All buffering and computation is performed internally in the FPGA. In terms of performance results, our architecture outperforms a general-purpose CPU running highly optimized software programmed in C by up to 51X; in neighborhoods up to 11X11 in which there are published results from GPUs our architecture has similar performance to GPUs at one-tenth the energy requirements, however, our architecture has the same performance for 29X29 neighborhoods whereas GPU performance drops as neighborhood grows. We expect this work to provide enabling new tools for the use of cellular automata models in the physical sciences.</efrbr-expression:summarizationOfContent><efrbr-expression:useRestrictionsOnTheExpression type="creative-commons">http://creativecommons.org/licenses/by/4.0/</efrbr-expression:useRestrictionsOnTheExpression><efrbr-expression:note type="page range">95-99</efrbr-expression:note><efrbr-expression:note type="conference name">29th International Conference on Field-Programmable Logic and Applications</efrbr-expression:note></efrbr-expression:expression><efrbr-person:person identifier="http://users.isc.tuc.gr/~nkyparissas"><efrbr-person:nameOfPerson vocabulary="TUC:LDAP">
            Kyparissas Nikolaos
            Κυπαρισσας Νικολαος
         </efrbr-person:nameOfPerson></efrbr-person:person><efrbr-person:person identifier="http://users.isc.tuc.gr/~adollas"><efrbr-person:nameOfPerson vocabulary="TUC:LDAP">
            Dollas Apostolos
            Δολλας Αποστολος
         </efrbr-person:nameOfPerson></efrbr-person:person><efrbr-corporateBody:corporateBody identifier="http://www.ieee.org/index.html"><efrbr-corporateBody:nameOfTheCorporateBody vocabulary="S/R:PUBLISHERS">
            Institute of Electrical and Electronics Engineers
         </efrbr-corporateBody:nameOfTheCorporateBody></efrbr-corporateBody:corporateBody><efrbr-concept:concept identifier="4AC50157-FAE0-4C58-A54E-463D46F9FB1F"><efrbr-concept:termForTheConcept>
            Cellular Automata
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="62C45507-03CA-4EBD-AB17-2A25A9F95F8F"><efrbr-concept:termForTheConcept>
            FPGA
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="D88B3784-8BF7-4317-A592-67AD27FBDD2A"><efrbr-concept:termForTheConcept>
            Large Neighborhood
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="13732A01-22CC-4086-857E-311ED463702E"><efrbr-concept:termForTheConcept>
            Real time
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