<efrbr:recordSet xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:efrbr="http://vfrbr.info/efrbr/1.1" xmlns:efrbr-work="http://vfrbr.info/efrbr/1.1/work" xmlns:efrbr-expression="http://vfrbr.info/efrbr/1.1/expression" xmlns:efrbr-manifestation="http://vfrbr.info/efrbr/1.1/manifestation" xmlns:efrbr-person="http://vfrbr.info/efrbr/1.1/person" xmlns:efrbr-corporateBody="http://vfrbr.info/efrbr/1.1/corporateBody" xmlns:efrbr-concept="http://vfrbr.info/efrbr/1.1/concept" xmlns:efrbr-structure="http://vfrbr.info/efrbr/1.1/structure" xmlns:efrbr-responsible="http://vfrbr.info/efrbr/1.1/responsible" xmlns:efrbr-subject="http://vfrbr.info/efrbr/1.1/subject" xmlns:efrbr-other="http://vfrbr.info/efrbr/1.1/other" xsi:schemaLocation="http://vfrbr.info/efrbr/1.1 http://vfrbr.info/schemas/1.1/efrbr.xsd"><efrbr:entities><efrbr-work:work identifier="http://purl.tuc.gr/dl/dias/3E0F8C3A-1AEC-4744-BFC1-51E75746F36E"><efrbr-work:titleOfTheWork>Charge-based modeling of long-channel symmetric double-gate junction FETs-Part I: drain current and transconductances</efrbr-work:titleOfTheWork></efrbr-work:work><efrbr-expression:expression identifier="http://purl.tuc.gr/dl/dias/3E0F8C3A-1AEC-4744-BFC1-51E75746F36E"><efrbr-expression:titleOfTheExpression>Charge-based modeling of long-channel symmetric double-gate junction FETs-Part I: drain current and transconductances</efrbr-expression:titleOfTheExpression><efrbr-expression:formOfExpression vocabulary="DIAS:TYPES">
            Peer-Reviewed Journal Publication
            Δημοσίευση σε Περιοδικό με Κριτές
         </efrbr-expression:formOfExpression><efrbr-expression:dateOfExpression type="issued">2019-09-03</efrbr-expression:dateOfExpression><efrbr-expression:dateOfExpression type="published">2018</efrbr-expression:dateOfExpression><efrbr-expression:languageOfExpression vocabulary="iso639-1">en</efrbr-expression:languageOfExpression><efrbr-expression:summarizationOfContent>The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of not only device fabrication but also its operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Physics-based compact models for JFETs, contrary to MOSFETs, are, however, scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, and transconductances of symmetric DG JFETs, covering all regions of device operation. The model is unified and continuous from subthreshold to linear and saturation operation and is valid over a large temperature range. This charge-based model constitutes the basis of a full compact model of the DG JFET.</efrbr-expression:summarizationOfContent><efrbr-expression:useRestrictionsOnTheExpression type="creative-commons">http://creativecommons.org/licenses/by/4.0/</efrbr-expression:useRestrictionsOnTheExpression><efrbr-expression:note type="journal name">IEEE Transactions on Electron Devices</efrbr-expression:note><efrbr-expression:note type="journal volume">65</efrbr-expression:note><efrbr-expression:note type="journal number">7</efrbr-expression:note><efrbr-expression:note type="page range">2744-2750</efrbr-expression:note></efrbr-expression:expression><efrbr-person:person identifier="http://users.isc.tuc.gr/~NMakris"><efrbr-person:nameOfPerson vocabulary="TUC:LDAP">
            Makris Nikolaos
            Μακρης Νικολαος
         </efrbr-person:nameOfPerson></efrbr-person:person><efrbr-person:person identifier="http://viaf.org/viaf/68145304358278570306"><efrbr-person:nameOfPerson vocabulary="VIAF">
            Jazaeri, Farzan 1984-
         </efrbr-person:nameOfPerson></efrbr-person:person><efrbr-person:person identifier="http://viaf.org/viaf/1057145857143022922975"><efrbr-person:nameOfPerson vocabulary="VIAF">
            Sallese, Jean-Michel 1964-
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            Sharma Rupendra Kumar
         </efrbr-person:nameOfPerson></efrbr-person:person><efrbr-person:person identifier="http://users.isc.tuc.gr/~mbucher"><efrbr-person:nameOfPerson vocabulary="TUC:LDAP">
            Bucher Matthias
            Bucher Matthias
         </efrbr-person:nameOfPerson></efrbr-person:person><efrbr-corporateBody:corporateBody identifier="http://www.ieee.org/index.html"><efrbr-corporateBody:nameOfTheCorporateBody vocabulary="S/R:PUBLISHERS">
            Institute of Electrical and Electronics Engineers
         </efrbr-corporateBody:nameOfTheCorporateBody></efrbr-corporateBody:corporateBody><efrbr-concept:concept identifier="1F345D7B-8E2C-4496-A565-AA40549443E3"><efrbr-concept:termForTheConcept>
            Analytical model
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="0619E42D-3180-46A8-A1AB-C720FD3A21AF"><efrbr-concept:termForTheConcept>
            Circuit simulation
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="1DC4F180-2D72-4679-B8B3-957DC3B4DDAD"><efrbr-concept:termForTheConcept>
            Compact model
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="488183F9-7C89-4A28-B369-6564FC579666"><efrbr-concept:termForTheConcept>
            JFET
            Junction field-effect transistor
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="AAA89184-11B6-4CE8-94ED-14D422F6274C"><efrbr-concept:termForTheConcept>
            Temperature effect
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