<efrbr:recordSet xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:efrbr="http://vfrbr.info/efrbr/1.1" xmlns:efrbr-work="http://vfrbr.info/efrbr/1.1/work" xmlns:efrbr-expression="http://vfrbr.info/efrbr/1.1/expression" xmlns:efrbr-manifestation="http://vfrbr.info/efrbr/1.1/manifestation" xmlns:efrbr-person="http://vfrbr.info/efrbr/1.1/person" xmlns:efrbr-corporateBody="http://vfrbr.info/efrbr/1.1/corporateBody" xmlns:efrbr-concept="http://vfrbr.info/efrbr/1.1/concept" xmlns:efrbr-structure="http://vfrbr.info/efrbr/1.1/structure" xmlns:efrbr-responsible="http://vfrbr.info/efrbr/1.1/responsible" xmlns:efrbr-subject="http://vfrbr.info/efrbr/1.1/subject" xmlns:efrbr-other="http://vfrbr.info/efrbr/1.1/other" xsi:schemaLocation="http://vfrbr.info/efrbr/1.1 http://vfrbr.info/schemas/1.1/efrbr.xsd"><efrbr:entities><efrbr-work:work identifier="http://purl.tuc.gr/dl/dias/2190DF60-9231-463F-8E6F-878E8B185832"><efrbr-work:titleOfTheWork>Charge-based model for junction FETs</efrbr-work:titleOfTheWork></efrbr-work:work><efrbr-expression:expression identifier="http://purl.tuc.gr/dl/dias/2190DF60-9231-463F-8E6F-878E8B185832"><efrbr-expression:titleOfTheExpression>Charge-based model for junction FETs</efrbr-expression:titleOfTheExpression><efrbr-expression:formOfExpression vocabulary="DIAS:TYPES">
            Peer-Reviewed Journal Publication
            Δημοσίευση σε Περιοδικό με Κριτές
         </efrbr-expression:formOfExpression><efrbr-expression:dateOfExpression type="issued">2019-09-02</efrbr-expression:dateOfExpression><efrbr-expression:dateOfExpression type="published">2018</efrbr-expression:dateOfExpression><efrbr-expression:languageOfExpression vocabulary="iso639-1">en</efrbr-expression:languageOfExpression><efrbr-expression:summarizationOfContent>We present a unified charge-based model for double-gate and cylindrical architectures of junction field-effect transistors (JFETs). The central concept is to consider the JFET as a junctionless FET (JLFET) with an infinitely thin insulating layer, leading to analytical expressions between charge densities, current, and voltages without any fitting parameters. Assessment of the model with numerical technology computer-aided design simulations confirms that holding the JFET as a special case of the JLFET is justified in all the regions of operation, i.e., from deep depletion to flat-band and from linear to saturation.</efrbr-expression:summarizationOfContent><efrbr-expression:useRestrictionsOnTheExpression type="creative-commons">http://creativecommons.org/licenses/by/4.0/</efrbr-expression:useRestrictionsOnTheExpression><efrbr-expression:note type="journal name">IEEE Transactions on Electron Devices</efrbr-expression:note><efrbr-expression:note type="journal volume">65</efrbr-expression:note><efrbr-expression:note type="journal number">7</efrbr-expression:note><efrbr-expression:note type="page range">2694-2698</efrbr-expression:note></efrbr-expression:expression><efrbr-manifestation:manifestation identifier="https://dias.library.tuc.gr/view/82984"><efrbr-manifestation:titleOfTheManifestation>Jazaeri_et_al_IEEE_Trans. Electron Devices_65(7)_2018.pdf</efrbr-manifestation:titleOfTheManifestation><efrbr-manifestation:publicationDistribution><efrbr-manifestation:placeOfPublicationDistribution type="distribution">Chania [Greece]</efrbr-manifestation:placeOfPublicationDistribution><efrbr-manifestation:publisherDistributor type="distributor">Library of TUC</efrbr-manifestation:publisherDistributor><efrbr-manifestation:dateOfPublicationDistribution>2019-08-30</efrbr-manifestation:dateOfPublicationDistribution></efrbr-manifestation:publicationDistribution><efrbr-manifestation:formOfCarrier>application/pdf</efrbr-manifestation:formOfCarrier><efrbr-manifestation:extentOfTheCarrier>2.1 MB</efrbr-manifestation:extentOfTheCarrier><efrbr-manifestation:accessRestrictionsOnTheManifestation>free</efrbr-manifestation:accessRestrictionsOnTheManifestation></efrbr-manifestation:manifestation><efrbr-person:person identifier="http://viaf.org/viaf/68145304358278570306"><efrbr-person:nameOfPerson vocabulary="VIAF">
            Jazaeri, Farzan 1984-
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            Makris Nikolaos
            Μακρης Νικολαος
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            Saeidi, Ali, 1973-
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            Bucher Matthias
            Bucher Matthias
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            Sallese, Jean-Michel 1964-
         </efrbr-person:nameOfPerson></efrbr-person:person><efrbr-corporateBody:corporateBody identifier="http://www.ieee.org/index.html"><efrbr-corporateBody:nameOfTheCorporateBody vocabulary="S/R:PUBLISHERS">
            Institute of Electrical and Electronics Engineers
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            Cylindrical gate all around junction field-effect transistor (JFET)
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="EE4038B5-D3FF-4706-946F-C836E6CD03F9"><efrbr-concept:termForTheConcept>
            Double-gate FETs
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="75611226-63F1-47A4-9DBD-9E173F80DB99"><efrbr-concept:termForTheConcept>
            Nanowire FETs
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="46305087-E8ED-4B6B-820F-3DD4E63122D9"><efrbr-concept:termForTheConcept>
            Power semiconductor FETs
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="742C2C5C-8200-40E8-AEFC-6105B008CD1D"><efrbr-concept:termForTheConcept>
            Radiation-hard electronics
         </efrbr-concept:termForTheConcept></efrbr-concept:concept><efrbr-concept:concept identifier="21B62049-7D10-48AE-A753-9F86AD9CF8D4"><efrbr-concept:termForTheConcept>
            Vertical JFET (V-JFET)
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