Investigation of scaling and temperature effects in total ionizing dose (TID) experiments in 65 nm CMOSInvestigation of scaling and temperature effects in total ionizing dose (TID) experiments in 65 nm CMOS Πλήρης Δημοσίευση σε Συνέδριο Conference Full Paper 2019-06-192018enTen-fold radiation levels are expected in the upgrade of the High-Luminosity Large Hadron Collider (HL-LHC) at CERN. Bulk silicon CMOS at 65 nm offers appreciable advantages among cost, performance, and resilience to high Total Ionizing Dose (TID). In the present paper, geometrical scaling of key analog design parameters of MOS transistors irradiated at high TID is investigated. Experiments are carried out for TID of 100, 200 and up to 500 Mrad(SiO2) and at -30°C, 0°C, and 25°C. We find that parameters are least degraded at -30°C. However, short-channel NMOSTs show a significant degradation of slope factor, which is more severe at 0°C than at 25°C. In contrast, the slope factor in short-channel PMOSTs shows lowest sensitivity to high TID.http://creativecommons.org/licenses/by/4.0/313-31825th International Conference ""Mixed Design of Integrated Circuits and Systems""Proceedings of 25th International Conference Mixed Design of Integrated Circuits and Systems Chevas Loukas Χεβας Λουκας Nikolaou Aristeidis Νικολαου Αριστειδης Bucher Matthias Bucher Matthias Makris Nikolaos Μακρης Νικολαος Papadopoulou Alexia Παπαδοπουλου Αλεξια Zografos Apostolos Ζωγραφος Αποστολος Borghello Giulio Koch Henri D. Faccio Federico Institute of Electrical and Electronics Engineers Analog parameter High Luminosity-Large Hadron Collider Ionizing radiation MOSFET Total ionizing dose (TID)