Modeling of high total ionizing dose (TID) effects for enclosed layout transistors in 65 nm bulk CMOSModeling of high total ionizing dose (TID) effects for enclosed layout transistors in 65 nm bulk CMOS Πλήρης Δημοσίευση σε Συνέδριο Conference Full Paper 2019-05-242018enHigh doses of ionizing radiation drastically impair the electrical performance of CMOS technology. Enclosed gate layout remains an effective means to reduce this impact. Nevertheless, high total ionizing dose (TID) effects remain strong. The paper presents an effective approach to analytically model high TID effects in both NMOS and PMOS transistors with enclosed-gate layout in 65 nm commercial CMOS.http://creativecommons.org/licenses/by/4.0/133-13641st International Semiconductor ConferenceProceedings of the International Semiconductor Conference Nikolaou Aristeidis Νικολαου Αριστειδης Bucher Matthias Bucher Matthias Makris Nikolaos Μακρης Νικολαος Papadopoulou Alexia Παπαδοπουλου Αλεξια Chevas Loukas Χεβας Λουκας Borghello Jiulio Koch Henri D. Faccio Federico Institute of Electrical and Electronics Engineers Compact modeling EKV model Enclosed gate MOSFETs High energy physics High total ionizing dose Radiation Space applications