<efrbr:recordSet xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:efrbr="http://vfrbr.info/efrbr/1.1" xmlns:efrbr-work="http://vfrbr.info/efrbr/1.1/work" xmlns:efrbr-expression="http://vfrbr.info/efrbr/1.1/expression" xmlns:efrbr-manifestation="http://vfrbr.info/efrbr/1.1/manifestation" xmlns:efrbr-person="http://vfrbr.info/efrbr/1.1/person" xmlns:efrbr-corporateBody="http://vfrbr.info/efrbr/1.1/corporateBody" xmlns:efrbr-concept="http://vfrbr.info/efrbr/1.1/concept" xmlns:efrbr-structure="http://vfrbr.info/efrbr/1.1/structure" xmlns:efrbr-responsible="http://vfrbr.info/efrbr/1.1/responsible" xmlns:efrbr-subject="http://vfrbr.info/efrbr/1.1/subject" xmlns:efrbr-other="http://vfrbr.info/efrbr/1.1/other" xsi:schemaLocation="http://vfrbr.info/efrbr/1.1 http://vfrbr.info/schemas/1.1/efrbr.xsd"><efrbr:entities><efrbr-work:work identifier="http://purl.tuc.gr/dl/dias/95931972-5301-4118-AD6D-D9AD1015F29C"><efrbr-work:titleOfTheWork>Implementation of an ARM processor with SIMD extensions using the Bluespec Hardware Description Language</efrbr-work:titleOfTheWork></efrbr-work:work><efrbr-expression:expression identifier="http://purl.tuc.gr/dl/dias/95931972-5301-4118-AD6D-D9AD1015F29C"><efrbr-expression:titleOfTheExpression>Implementation of an ARM processor with SIMD extensions using the Bluespec Hardware Description Language</efrbr-expression:titleOfTheExpression><efrbr-expression:titleOfTheExpression>Υλοποίηση επεξεργαστή ARM με επέκταση εντολών SIMD με χρήση Γλώσσας Περιγραφής Υλικού Bluespec </efrbr-expression:titleOfTheExpression><efrbr-expression:formOfExpression vocabulary="DIAS:TYPES">
            Διπλωματική Εργασία
            Diploma Work
         </efrbr-expression:formOfExpression><efrbr-expression:dateOfExpression type="issued">2018-05-17</efrbr-expression:dateOfExpression><efrbr-expression:dateOfExpression type="published">2018</efrbr-expression:dateOfExpression><efrbr-expression:languageOfExpression vocabulary="iso639-1">en</efrbr-expression:languageOfExpression><efrbr-expression:summarizationOfContent>The goal of this thesis was to implement an ARM processor with Single Instruction Multiple Data (SIMD) extensions using the Bluespec System Verilog (BSV) as a Hardware Description Language (HDL). BSV has a fundamentally different approach to hardware design, comparing to other HDLs. It is based on circuit generation - rather than merely circuit description - and on atomic transactional rules instead of a globally synchronous view of the world. BSV language is considered a high-level functional HDL, which was essentially Haskell - extended to handle chip design and electronic design automation in general. BSV is partially evaluated (to convert the Haskell parts) and compiled to the Term Rewriting System (TRS). Our scalar processor supports a 3-stage pipeline (Fetch – Decode – Execute), belongs to the ARM7 family and uses a 32-bit architecture, which is based on ARMv4 instruction set. The SIMD unit works as an extension to the scalar part and is based on a modification of ARM NEON technology. The scalar part of the processor supports Data processing, Multiply, Long Multiply, Load/Store – Byte/Word and Branch instructions of the ARM Instruction Set Format, while the vector part supports Vector Data Processing, Vector Multiply and Vector Load/Store instructions.</efrbr-expression:summarizationOfContent><efrbr-expression:useRestrictionsOnTheExpression type="creative-commons">http://creativecommons.org/licenses/by/4.0/</efrbr-expression:useRestrictionsOnTheExpression><efrbr-expression:note type="academic unit">Πολυτεχνείο Κρήτης::Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών</efrbr-expression:note></efrbr-expression:expression><efrbr-manifestation:manifestation identifier="http://purl.tuc.gr/dl/dias/9FD321CD-22A5-46BF-A072-7BF92ECDA52E"><efrbr-manifestation:titleOfTheManifestation>Makrygiannis_Konstantinos_Dip_2018.pdf</efrbr-manifestation:titleOfTheManifestation><efrbr-manifestation:publicationDistribution><efrbr-manifestation:placeOfPublicationDistribution type="distribution">Chania [Greece]</efrbr-manifestation:placeOfPublicationDistribution><efrbr-manifestation:publisherDistributor type="distributor">Library of TUC</efrbr-manifestation:publisherDistributor><efrbr-manifestation:dateOfPublicationDistribution>2018-05-17</efrbr-manifestation:dateOfPublicationDistribution></efrbr-manifestation:publicationDistribution><efrbr-manifestation:formOfCarrier>application/pdf</efrbr-manifestation:formOfCarrier><efrbr-manifestation:extentOfTheCarrier>3.9 MB</efrbr-manifestation:extentOfTheCarrier><efrbr-manifestation:accessRestrictionsOnTheManifestation>free</efrbr-manifestation:accessRestrictionsOnTheManifestation></efrbr-manifestation:manifestation><efrbr-person:person identifier="http://users.isc.tuc.gr/~kmakrygiannis"><efrbr-person:nameOfPerson vocabulary="TUC:LDAP">
            Makrygiannis Konstantinos
            Μακρυγιαννης Κωνσταντινος
         </efrbr-person:nameOfPerson></efrbr-person:person><efrbr-person:person identifier="http://users.isc.tuc.gr/~dpnevmatikatos"><efrbr-person:nameOfPerson vocabulary="TUC:LDAP">
            Pnevmatikatos Dionysios
            Πνευματικατος Διονυσιος
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            Dollas Apostolos
            Δολλας Αποστολος
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            Theodoropoulos Dimitrios
            Θεοδωροπουλος Δημητριος
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            Πολυτεχνείο Κρήτης
            Technical University of Crete
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            Bluespec
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            Vector processing
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            ARM
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