An architecture for the acceleration of a hybrid leaky integrate and fire SNN on the convey HC-2ex FPGA-based processorAn architecture for the acceleration of a hybrid leaky integrate and fire SNN on the convey HC-2ex FPGA-based processor Πλήρης Δημοσίευση σε Συνέδριο Conference Full Paper 2018-05-082017enNeuromorphic computing is expanding by leaps and bounds through custom integrated circuits (digital and analog), and large scale platforms developed by industry or government-funded projects (e.g. TrueNorth and BrainScaleS, respectively). Whereas the trend is for massive parallelism and neuromorphic computation in order to solve problems, such as those that may appear in machine learning and deep learning algorithms, there is substantial work on brain-like highly accurate neuromorphic computing in order to model the human brain. In such a form of computing, spiking neural networks (SNN) such as the Hodgkin and Huxley model are mapped to various technologies, including FPGAs. In this work, we present a highly efficient FPGA-based architecture for the detailed hybrid Leaky Integrate and Fire SNN that can simulate generic characteristics of neurons of the cerebral cortex. This architecture supports arbitrary, sparse O(n2) interconnection of neurons without need to re-compile the design, and plasticity rules, yielding on a four-FPGA Convey 2ex hybrid computer a speedup of 923x for a non-trivial data set on 240 neurons vs. the same model in the software simulator BRAIN on a Intel(R) Xeon(R) CPU E5-2620 v2 @ 2.10GHz, i.e. the reference state-of-the-art software. Although the reference, official software is single core, the speedup demonstrates that the application scales well among multiple FPGAs, whereas this would not be the case in general-purpose computers due to the arbitrary interconnect requirements. The FPGA-based approach leads to highly detailed models of parts of the human brain up to a few hundred neurons vs. a dozen or fewer neurons on the reference system.http://creativecommons.org/licenses/by/4.0/56-63IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines25th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines Kousanakis Emmanouil Κουσανακης Εμμανουηλ Dollas Apostolos Δολλας Αποστολος Sotiriadis Evripidis Σωτηριαδης Ευριπιδης Papaefstathiou Ioannis Παπαευσταθιου Ιωαννης Pnevmatikatos Dionysios Πνευματικατος Διονυσιος Papoutsi Athanasia Παπουτση Αθανασια Πετραντωνάκης Παναγιώτης Κ. Petrantonakis Panagiotis C. Poirazi Panagiota Ποιραζη Παναγιωτα Χαυλής Σπυρίδων Chavlis Spyridon Καστελλάκης Γεώργιος Kastellakis George Institute of Electrical and Electronics Engineers BCM rule FPGA Homeostatic plasticity Leaky integrate and fire model Simulation speedup Spiking neural networks