<efrbr:recordSet xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:efrbr="http://vfrbr.info/efrbr/1.1" xmlns:efrbr-work="http://vfrbr.info/efrbr/1.1/work" xmlns:efrbr-expression="http://vfrbr.info/efrbr/1.1/expression" xmlns:efrbr-manifestation="http://vfrbr.info/efrbr/1.1/manifestation" xmlns:efrbr-person="http://vfrbr.info/efrbr/1.1/person" xmlns:efrbr-corporateBody="http://vfrbr.info/efrbr/1.1/corporateBody" xmlns:efrbr-concept="http://vfrbr.info/efrbr/1.1/concept" xmlns:efrbr-structure="http://vfrbr.info/efrbr/1.1/structure" xmlns:efrbr-responsible="http://vfrbr.info/efrbr/1.1/responsible" xmlns:efrbr-subject="http://vfrbr.info/efrbr/1.1/subject" xmlns:efrbr-other="http://vfrbr.info/efrbr/1.1/other" xsi:schemaLocation="http://vfrbr.info/efrbr/1.1 http://vfrbr.info/schemas/1.1/efrbr.xsd"><efrbr:entities><efrbr-work:work identifier="http://purl.tuc.gr/dl/dias/AA74171F-9466-47DA-B700-F584A6974AB9"><efrbr-work:titleOfTheWork>Modeling recursion data structures for FPGA-based implementation</efrbr-work:titleOfTheWork></efrbr-work:work><efrbr-expression:expression identifier="http://purl.tuc.gr/dl/dias/AA74171F-9466-47DA-B700-F584A6974AB9"><efrbr-expression:titleOfTheExpression>Modeling recursion data structures for FPGA-based implementation</efrbr-expression:titleOfTheExpression><efrbr-expression:formOfExpression vocabulary="DIAS:TYPES">
            Δημοσίευση σε Συνέδριο
            Conference Publication
         </efrbr-expression:formOfExpression><efrbr-expression:dateOfExpression type="issued">2015-11-17</efrbr-expression:dateOfExpression><efrbr-expression:dateOfExpression type="published">2008</efrbr-expression:dateOfExpression><efrbr-expression:languageOfExpression vocabulary="iso639-1">en</efrbr-expression:languageOfExpression><efrbr-expression:summarizationOfContent>Recursion is a powerful technique used to solve problems with repeating patterns, and is a fundamental structure in software. To date there is no known general way to apply a recursive solution to reconfigurable hardware; it is considered difficult to implement, of low performance and resource-intensive. In this paper we extend previous results on hardware structures for recursion by V. Sklyarov, and we demonstrate that recursion can be efficiently implemented in a general way on FPGAs. We show that our general, non-optimized architecture presents approximately 3 times speedup against optimized software algorithm implementations. It also shows 75% speedup, at least 40% lower area utilization, and at the same time it is simpler, less designer time consuming and more general vs. previously published hardware implementations.</efrbr-expression:summarizationOfContent><efrbr-expression:useRestrictionsOnTheExpression type="creative-commons">http://creativecommons.org/licenses/by/4.0/</efrbr-expression:useRestrictionsOnTheExpression><efrbr-expression:note type="page range">11-16</efrbr-expression:note><efrbr-expression:note type="conference name">International Conference on Field Programmable Logic and Applications</efrbr-expression:note></efrbr-expression:expression><efrbr-person:person identifier="http://users.isc.tuc.gr/~spninos"><efrbr-person:nameOfPerson vocabulary="TUC:LDAP">
            Ninos Spyridon
            Νινος Σπυριδων
         </efrbr-person:nameOfPerson></efrbr-person:person><efrbr-person:person identifier="http://users.isc.tuc.gr/~adollas"><efrbr-person:nameOfPerson vocabulary="TUC:LDAP">
            Dollas Apostolos
            Δολλας Αποστολος
         </efrbr-person:nameOfPerson></efrbr-person:person><efrbr-corporateBody:corporateBody identifier="http://www.ieee.org/index.html"><efrbr-corporateBody:nameOfTheCorporateBody vocabulary="S/R:PUBLISHERS">
            Institute of Electrical and Electronics Engineers
         </efrbr-corporateBody:nameOfTheCorporateBody></efrbr-corporateBody:corporateBody><efrbr-concept:concept identifier="http://id.loc.gov/authorities/subjects/sh93009062"><efrbr-concept:termForTheConcept>
            Field programmable logic arrays
            FPGAs
            field programmable gate arrays
            field programmable logic arrays
            fpgas
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