An FPGA-based sudoku solver based on simulated annealing methodsAn FPGA-based sudoku solver based on simulated annealing methods Δημοσίευση σε Συνέδριο Conference Publication 2015-11-172009enThe Sudoku simulated annealing solver -SSAS is a probabilistic Sudoku solver. The general design is capable of solving a Sudoku board of order up to fifteen (15 × 15 × 15 × 15). It has been designed and fully implemented on a Xilinx Virtex II Pro - based Digilent XUP board. The solver has a serial-port interface to download problems and upload results to a personal computer, according to the specifications of the relevant competition of the 2009 International Conference on Field Programmable Technology (FPT). The SSAS has solved in actual hardware Sudoku puzzles of up to order 12 within the competition-imposed time limits.http://creativecommons.org/licenses/by/4.0/522-525International Conference on Field-Programmable Technology Malakonakis Pavlos Μαλακωνακης Παυλος Smerdis Miltiadis Σμερδης Μιλτιαδης Sotiriadis Evripidis Σωτηριαδης Ευριπιδης Dollas Apostolos Δολλας Αποστολος Institute of Electrical and Electronics Engineers Field programmable logic arrays FPGAs field programmable gate arrays field programmable logic arrays fpgas