Exploring FPGAs for accelerating the phylogenetic likelihood functionExploring FPGAs for accelerating the phylogenetic likelihood function Δημοσίευση σε Συνέδριο Conference Publication 2015-11-172009enDriven by novel biological wet lab techniques such as pyrosequencing there has been an unprecedented molecular data explosion. The growth of biological sequence data has significantly out-paced Moore's law. This development also poses new computational and architectural challenges for the field of phylogenetic inference, i.e., the reconstruction of evolutionary histories (trees) for a set of organisms which are represented by respective molecular sequences. Phylogenetic trees are currently increasingly reconstructed from multiple genes or even whole genomes. The introduced term "phylogenomics" reflects this development. Hence, there is an urgent need to deploy and develop new techniques and computational solutions to calculate the computationally intensive scoring functions for phylogenetic trees. In this paper, we propose a dedicated computer architecture to compute the phylogenetic maximum likelihood (ML) function. The ML criterion represents one of the most accurate statistical models for phylogenetic inference and accounts for 85% to 95% of total execution time in all state-of-the-art ML-based phylogenetic inference programs. We present the implementation of our architecture on an FPGA (field programmable gate array) and compare the performance to an efficient C implementation of the ML function on a high-end multi-core architecture with 16 cores. Our results are two-fold: (i) the initial exploratory implementation of the ML function for trees comprising 4 up to 512 sequences on an FPGA yields speedups of a factor 8.3 on average compared to execution on a single-core and is faster than the OpenMP-based parallel implementation on up to 16 cores in all but one case; and (ii) we are able to show that current FPGAs are capable to efficiently execute floating point intensive computational kernels.http://creativecommons.org/licenses/by/4.0/1-8IEEE International Symposium on Parallel and Distributed Processing Alachiotis, Nikolaos Sotiriadis Evripidis Σωτηριαδης Ευριπιδης Dollas Apostolos Δολλας Αποστολος Stamatakis Alexandros Σταματακης Αλεξανδρος Institute of Electrical and Electronics Engineers Automatic computers Automatic data processors Computer hardware Computing machines (Computers) Electronic brains Electronic calculating-machines Electronic computers Hardware, Computer computers automatic computers automatic data processors computer hardware computing machines computers electronic brains electronic calculating machines electronic computers hardware computer