Hardware-software codesign and parallel implementation of a golomb ruler derivation engineHardware-software codesign and parallel implementation of a golomb ruler derivation engine Δημοσίευση σε Συνέδριο Conference Publication 2015-11-172000enA new architecture for Golomb ruler derivation has been developed so that rulers up to 24 marks can be proven on it. In this architecture, 8-mark stubs that are derived on a personal computer are subsequently processed by the FCCM, called GE2, allowing for parallel processing of as many stubs as are the available FPGAs. Actual runs of the new design have been performed on the TOP parallel FPGA machine at Virginia Tech. This paper presents the design improvements over the original architecture, which include single FPGA implementation, hardware/software codesign, FIFO based I/O, design for parallel execution, and performance results from actual runs.http://creativecommons.org/licenses/by/4.0/227-2358th International IEEE Symposium on Field-Programmable Custom Computing MachinesProceedings, 8th International IEEE Symposium on Field-Programmable Custom Computing Machines Sotiriadis Evripidis Σωτηριαδης Ευριπιδης Dollas Apostolos Δολλας Αποστολος Athanas Peter Institute of Electrical and Electronics Engineers Computers--Programming Electronic computer programming Electronic data processing--Programming Electronic digital computers--Programming Programming (Electronic computers) computer programming computers programming electronic computer programming electronic data processing programming electronic digital computers programming programming electronic computers