Scheduling components for multi-gigabit network SoCsScheduling components for multi-gigabit network SoCs Πλήρης Δημοσίευση σε Συνέδριο Conference Full Paper 2015-11-162003enTo meet the demand for higher performance, flexibility, and economy in today's state-of-the-art networks, great emphasis is placed on unconventional hardware architectures of network processors. This paper analyzes the problem of processor internal resource and traffic management and proposes a programmable scheduler architecture implemented in a novel protocol processor (PRO3) that deals with the above problems in an integrated way. We briefly outline the architecture of the protocol processor and we support that the innovative scheduling scheme integrated in PR03 is, in general, crucial for network Systems-on-Chip (SoCs) since it makes it feasible to use external memories for scheduling and still accommodate multi-gigabit network speeds. Extensions to the PRO3 scheduler's architecture are discussed that lead to efficient integration of the component to different network processor architectures at a similar cost. Its beneficial features are easy hardware implementation, low memory bandwidth requirements and high flexibility so as to support multiple service disciplines in a programmable way, thousands of flows and even perform different scheduling tasks.http://creativecommons.org/licenses/by/4.0/2003 SPIE First International Symposium on Microtechnologies for the New Millennium 2003C16_spie03_NPUsched.pdfChania [Greece]Library of TUC2015-11-16application/pdf374.3 kBfree Papaefstathiou Ioannis Παπαευσταθιου Ιωαννης Kornaros Georgios Κορναρος Γεωργιος Orphanoudakis T. Leligou H. Perissakis S. Zervos N.