A reconfigurable logic-based processor for the SCAN image and video encryption algorithmA reconfigurable logic-based processor for the SCAN image and video encryption algorithm Peer-Reviewed Journal Publication Δημοσίευση σε Περιοδικό με Κριτές 2015-11-142003enThis paper presents a detailed architecture and a reconfigurable logic based hardware design of the SCAN algorithm. This architecture can be used to encrypt high resolution images in real-time. Although the SCAN algorithm is a block cipher algorithm with arbitrarily large blocks, the present design is for 64×64 pixel blocks in order to provide real-time image encryption throughput. The architecture was initially targeted at the Xilinx XCV-1000 FPGA, for which design and performance results are presented in the paper.http://creativecommons.org/licenses/by/4.0/International Journal of Parallel Programming316489-506 Dollas Apostolos Δολλας Αποστολος Bourbakis, Nikolaos G Kachris, Christoforos Kluwer Reconfigurable logic Image encryption Block cipher Cryptography