The evolution of instruction sequencingThe evolution of instruction sequencing Peer-Reviewed Journal Publication Δημοσίευση σε Περιοδικό με Κριτές 2015-11-031991enThe three distinct phases that constitute the sequencing of an instruction are determining the memory address that contains the instruction, fetching the instruction from memory, and executing the instruction. The evolution of instruction sequencing is traced, with attention focused on the influence of the available technology on the minimum time required for each of these phases and the resulting design decisions. Rather than absolute system performance. the interrelationship of these critical parameters is examined. Memory bandwidth, instruction buffers, caches, and the impact of reduced-instruction-set computers (RISCs) are discussed. Recent innovations are described, and the options and constraints that designers face with respect to future developments are evaluated.http://creativecommons.org/licenses/by/4.0/Computer2445-15 Krick R. F. Dollas Apostolos Δολλας Αποστολος Institute of Electrical and Electronics Engineers Bandwidth Random access memory Interleaved codes Tellurium Magnetic cores Semiconductor memory Bipolar transistors System performance Terminology Context modeling