Predicting and precluding problems with memory latencyPredicting and precluding problems with memory latency Peer-Reviewed Journal Publication Δημοσίευση σε Περιοδικό με Κριτές 2015-11-021994enBy examining the rate at which successive generations of processor and DRAM cycle times have been diverging over time, we can track the latency problem of computer memory systems. Our research survey starts with the fundamentals of single-level caches and moves to the need for multilevel cache hierarchies. We look at some of the current techniques for boosting cache performance, especially compiler-based methods for code restructuring and instruction and data prefetching. These two areas will likely yield improvements for a much larger domain of applications in the future.http://creativecommons.org/licenses/by/4.0/IEEE Micro14459-67 Boland K. Dollas Apostolos Δολλας Αποστολος Institute of Electrical and Electronics Engineers Delay Random access memory Throughput Clocks Microprocessors Content addressable storage Boosting Prefetching Application software Microcomputers