An effective framework to evaluate dynamic partial reconfiguration in FPGA systemsAn effective framework to evaluate dynamic partial reconfiguration in FPGA systems Peer-Reviewed Journal Publication Δημοσίευση σε Περιοδικό με Κριτές 2015-11-022010enThe most popular representative devices of reconfigurable computing are field-programmable gate arrays (FPGAs). A promising feature of an FPGA is the ability to reuse the same hardware for different tasks at different phases of an application execution. Moreover, the tasks can be swapped on the fly while part of the hardware continues to operate. This is known as dynamic reconfiguration, and evaluation of its performance presents interesting research challenges. This paper introduces a general framework for measuring the reconfiguration time from the system perspective. In addition, a methodology for setting up different system parameters and automatically gathering and processing the experimental results has been developed. It is proven that these parameters affect the applications designed in a dynamically reconfigurable system, and rapid evaluation enables quick examination of their impact on performance. Results demonstrate the usefulness of the framework.http://creativecommons.org/licenses/by/4.0/IEEE Transactions on Instrumentation and Measurement5961642-1651 Papadimitriou Kyprianos Παπαδημητριου Κυπριανος Anyfantis Antonis Dollas Apostolos Δολλας Αποστολος Institute of Electrical and Electronics Engineers Field programmable gate arrays Programmable logic arrays Hardware Random access memory Application software Protocols Time measurement Reconfigurable architectures System analysis and design Circuits