ATLAS II: οptimizing a 10Gbps σingle-chip ATM switchATLAS II: οptimizing a 10Gbps σingle-chip ATM switch Αφίσα σε Συνέδριο Conference Poster 2015-10-191999enWe describe ATLAS II, an optimized version of the ATLAS I ATM switch. While in ATLAS I we concentrated on correctness, in ATLAS II we concentrate on optimizing the area and the performance of the switch. To achieve these goals we utilize improved design techniques and circuitry, and we eliminate functionalities of marginal benefit. Our results show that we can achieve significant performance and cost benefits, requiring only a small increment in manpower http://creativecommons.org/licenses/by/4.0/12th Annual 1999 IEEE International ASIC/SOC Conference Pnevmatikatos Dionysios Πνευματικατος Διονυσιος George Kornaros