An efficient and low-cost input/output subsystem for network processorsAn efficient and low-cost input/output subsystem for network processors Peer-Reviewed Journal Publication Δημοσίευση σε Περιοδικό με Κριτές 2015-10-192003enWe present the architecture and implementation of an input/output subsystem for a cost-effective network processor. We believe that adding processing power to a networking chip is relatively straightforward. However, transferring data to and from the processor(s) is insufficient for high wire speeds. To address this limitation we use a hardwired input/output subsystem transferring data directly into the processing core’s register file. Using a simple scalar RISC core at 200MHz, we are able to sustain state-full inspection firewall processing at 2.5Gbps TCP traffic.http://creativecommons.org/licenses/by/4.0/IEEE Design and Test of Computers42056-64 Pnevmatikatos Dionysios Πνευματικατος Διονυσιος Kyriakos Vlachos Ioannis Sourdis Monitoring of computer networks Network monitoring (Computer networks) computer networks monitoring monitoring of computer networks network monitoring computer networks