<efrbr:recordSet xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:efrbr="http://vfrbr.info/efrbr/1.1" xmlns:efrbr-work="http://vfrbr.info/efrbr/1.1/work" xmlns:efrbr-expression="http://vfrbr.info/efrbr/1.1/expression" xmlns:efrbr-manifestation="http://vfrbr.info/efrbr/1.1/manifestation" xmlns:efrbr-person="http://vfrbr.info/efrbr/1.1/person" xmlns:efrbr-corporateBody="http://vfrbr.info/efrbr/1.1/corporateBody" xmlns:efrbr-concept="http://vfrbr.info/efrbr/1.1/concept" xmlns:efrbr-structure="http://vfrbr.info/efrbr/1.1/structure" xmlns:efrbr-responsible="http://vfrbr.info/efrbr/1.1/responsible" xmlns:efrbr-subject="http://vfrbr.info/efrbr/1.1/subject" xmlns:efrbr-other="http://vfrbr.info/efrbr/1.1/other" xsi:schemaLocation="http://vfrbr.info/efrbr/1.1 http://vfrbr.info/schemas/1.1/efrbr.xsd"><efrbr:entities><efrbr-work:work identifier="http://purl.tuc.gr/dl/dias/6046BEE3-CF4C-499F-B956-DB3163DBD5AC"><efrbr-work:titleOfTheWork>Multisplitting iterative methods on fixed-size VLSI architectures</efrbr-work:titleOfTheWork></efrbr-work:work><efrbr-expression:expression identifier="http://purl.tuc.gr/dl/dias/6046BEE3-CF4C-499F-B956-DB3163DBD5AC"><efrbr-expression:titleOfTheExpression>Multisplitting iterative methods on fixed-size VLSI architectures</efrbr-expression:titleOfTheExpression><efrbr-expression:formOfExpression vocabulary="DIAS:TYPES">
            Peer-Reviewed Journal Publication
            Δημοσίευση σε Περιοδικό με Κριτές
         </efrbr-expression:formOfExpression><efrbr-expression:dateOfExpression type="issued">2015-10-16</efrbr-expression:dateOfExpression><efrbr-expression:dateOfExpression type="published">1995</efrbr-expression:dateOfExpression><efrbr-expression:languageOfExpression vocabulary="iso639-1">en</efrbr-expression:languageOfExpression><efrbr-expression:summarizationOfContent>Multisplitting Iterative Methods is a parametrizable family of iterative methods capable of solving Large Linear Systems. They are formed by the proper weighted average of classical (or not) iterative schemes. Hence, they present a second level of inherent parallelism while, at the same time, they take advantage of the parallel hardware to decrease both the computational time and the number of iterations involved in the computation. The increasingly large size of linear systems and the consideration of realistically large, but fixed-size, VLSI architectures, for their solution, motivated this work. We design new fixed size VLSI modules, based on space-time partitioning techniques, to efficiently resolve the problems arising in the computation of an oversized iteration step.</efrbr-expression:summarizationOfContent><efrbr-expression:useRestrictionsOnTheExpression type="creative-commons">http://creativecommons.org/licenses/by/4.0/</efrbr-expression:useRestrictionsOnTheExpression><efrbr-expression:note type="journal name">Computing Systems in Engineering</efrbr-expression:note><efrbr-expression:note type="journal volume">4-5</efrbr-expression:note><efrbr-expression:note type="journal number">6</efrbr-expression:note><efrbr-expression:note type="page range">477–484</efrbr-expression:note></efrbr-expression:expression><efrbr-person:person identifier="http://users.isc.tuc.gr/~gsaridakis"><efrbr-person:nameOfPerson vocabulary="TUC:LDAP">
            Saridakis Ioannis
            Σαριδακης Ιωαννης
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            Papadopoulou Eleni
            Παπαδοπουλου Ελενη
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            Elsevier
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            Greek mathematics
            mathematics greek
            greek mathematics
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