The best of many worlds: scheduling machine learning inference on CPU-GPU integrated architecturesThe best of many worlds: scheduling machine learning inference on CPU-GPU integrated architectures Πλήρης Δημοσίευση σε Συνέδριο Conference Full Paper 2024-07-312022enA plethora of applications are using machine learning, the operations of which are becoming more complex and require additional computing power. At the same time, typical commodity system setups (including desktops, servers, and embedded devices) are now offering different processing devices, the most often of which are multi-core CPUs, integrated GPUs, and discrete GPUs. In this paper, we follow a data-driven approach, where we first show the performance of different processing devices when executing a diversified set of inference engines; some processing devices perform better for different performance metrics (e.g., throughput, latency, and power consumption), while at the same time, these metrics may also deviate significantly among different applications. Based on these findings, we propose an adaptive scheduling approach, tailored for machine learning inference operations, that enables the use of the most efficient processing device available. Our scheduler is device-agnostic and can respond quickly to dynamic fluctuations that occur at real-time, such as data bursts, application overloads and system changes. The experimental results show that it is able to match the peak throughput, by predicting correctly the optimal processing device with an accuracy of 92.5%, with energy savings up to 10%.This work was supported by the projects CONCORDIA, C4IIoT, COLLABS, and MARVEL funded by the European Commission under Grant Agreements No. 830927, No. 833828, No. 871518, and No. 957337.http://creativecommons.org/licenses/by-nc-nd/4.0/55-642022 IEEE International Parallel and Distributed Processing Symposium WorkshopsProceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2022)Vasiliadis_et_al_IPDPSW_2022_preprint.pdfChania [Greece]Library of TUC2024-07-31application/pdf828.3 kBfree Vasiliadis Giorgos Tsirbas Rafail Ioannidis Sotirios Ιωαννιδης Σωτηριος Institute of Electrical and Electronics Engineers Machine learning algorithms Computer architecture Performance evaluation