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Feature reduction for FPGA based implementation of learning classifiers

Vogiatzis Konstantinos

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Summary

During recent years data sets have grown rapidly in size, mainly becausethey are collectively gathered by numerous consumer information-sensinginternet of things (IoT) devices or services, such as mobile devices, softwarelogs, cameras, wireless sensor networks, etc. Heterogeneous hardware, suchas FPGAs, seem to be a promising alternative in terms of acceleration, evenfrom GPUs, in complex machine learning problems. They still suffer thoughfrom low on-chip memory resources making scaling to high dimensionalitytasks difficult, as input/output (I/O) traffic may dominate the overalllatency. Due to such restrictions, FPGAs currently, are mostly used for theinference task and not the training one, as it usually requires fewer memoryresources. In this work, we propose a general dimensionality reductionscheme for learning classifiers, operating both as training and inference accelerators which could be applied in low resource hardware devices, suchas FPGAs. We achieve impressive improvements, with on-chip memory utilizationduring training reduced by 10× to 32× for online and batch learning,with around 5% loss in accuracy. We implement a pipelined hardware architecture,using a learning classifier coupled with a dimensionality reduction scheme implementing two different methods: Hash Kernel and Sparse Random Projection.

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