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Design in HDL of a DMA engine that complies with the AMBA 5 CHI communication protocol

Kourkoulos Angelos

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Summary

A Direct Memory Access (DMA) is a system that allows a device to transfer data directly to and from main memory, bypassing the central processing unit (CPU). This can be useful for transferring quickly large amounts of data, as it allows the CPU to perform other tasks while the DMA controller handles the data transfer. The aim of this thesis is to design, optimize and verify in HDL an IP Core (Intellectual Property Core) DMA engine that complies with AMBA 5 CHI(Coherent Hub Interface) protocol and efficiently transfers data to and from the CHI hub which can be used in HPC (High-Performance Computing) to improve the performance. This DMA controller is designed to be able to handle a scalable amount of memory transfers, generically schedule them based on the user’s demands and transfer the appropriate data at any address byte offset in memory. The proposed DMA is designed to work with systems that use AMBA 5 CHI architecture as it is a state-of-the-art technology designed by ARM that classifies different components in a system by node type and provides a means for communication between nodes. CHI is designed for High bandwidth, efficiency, scalability, and reliability, while it offers the capability for memory and cache coherency which are the basic reasons that CHI is widely used in HPC. By complying with this protocol, the presented IP Core can utilize the advantages that CHI provides as well as the features of the DMA architecture and be a useful tool to improve the performance of systems that would incorporate it.

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