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Reconfigurable logic (FPGA)-based system architecture for the acceleration of federated learning in neural networks

Petrakos Emmanouil

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Summary

Federated Learning (FL) is a decentralized training method for Machine Learning applications which can exploit data that are inaccessible to conventional centralized approaches, due to privacy and security concerns. FL literature has refined and evaluated most of its aspects, but generally few works have taken into consideration the underlying hardware, where the training actually takes place.This thesis demonstrates that, in the on-edge FL setting, the clients can effectively utilize FPGAs to accelerate their local training and the overall FL process. First, an FL system, agnostic of the underlying training method and its implementation, is developed. With that, an in-depth analysis of the effects of each FL parameter is conducted. According to its findings, an FPGA-based implementation of a Convolutional Neural Network (CNN), optimized for the parameter space where the FL is most efficient, is developed and incorporated into the FL system.Through actual runs on real hardware, the FPGA-based solution presents a modest speedup of the local training (1.27$\times$-1.44$\times$) and the overall FL process (1.08$\times$-1.20$\times$) in comparison to a GPU-based one, depending on data distribution. More impressively, it consumes (16.35$\times$-18.18$\times$) less energy. Thus, this thesis provides more than a feasibility study of combining FL and FPGAs, and it can be used as a starting point for future works or as a benchmarking reference.

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