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MC-DeF: creating customized CGRAs for dataflow applications

Charitopoulos Georgios, Pnevmatikatos Dionysios, Gaydadjiev, Georgi

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URIhttp://purl.tuc.gr/dl/dias/BE27CF42-F1DF-4FF8-84F3-151358B50415-
Αναγνωριστικόhttps://doi.org/10.1145/3447970-
Αναγνωριστικόhttps://dl.acm.org/doi/10.1145/3447970-
Γλώσσαen-
Μέγεθος25 pagesen
ΤίτλοςMC-DeF: creating customized CGRAs for dataflow applicationsen
ΔημιουργόςCharitopoulos Georgiosen
ΔημιουργόςΧαριτοπουλος Γεωργιοςel
ΔημιουργόςPnevmatikatos Dionysiosen
ΔημιουργόςΠνευματικατος Διονυσιοςel
ΔημιουργόςGaydadjiev, Georgien
ΕκδότηςAssociation for Computing Machinery (ACM)en
ΠερίληψηExecuting complex scientific applications on Coarse-Grain Reconfigurable Arrays (CGRAs) promises improvements in execution time and/or energy consumption compared to optimized software implementations or even fully customized hardware solutions. Typical CGRA architectures contain of multiple instances of the same compute module that consist of simple and general hardware units such as ALUs, simple processors. However, generality in the cell contents, while convenient for serving a wide variety of applications, penalizes performance and energy efficiency. To that end, a few proposed CGRAs use custom logic tailored to a particular application’s specific characteristics in the compute module. This approach, while much more efficient, restricts the versatility of the array. To date, versatility at hardware speeds is only supported with Field programmable gate arrays (FPGAs), that are reconfigurable at a very fine grain. This work proposes MC-DeF, a novel Mixed-CGRA Definition Framework targeting a Mixed-CGRA architecture that leverages the advantages of CGRAs by utilizing a customized cell array, and those of FPGAs by incorporating a separate LUT array used for adaptability. The framework presented aims to develop a complete CGRA architecture. First, a cell structure and functionality definition phase creates highly customized application/domain specific CGRA cells. Then, mapping and routing phases define the CGRA connectivity and cell-LUT array transactions. Finally, an energy and area estimation phase presents the user with area occupancy and energy consumption estimations of the final design. MC-DeF uses novel algorithms and cost functions driven by user defined metrics, threshold values, and area/energy restrictions. The benefits of our framework, besides creating fast and efficient CGRA designs, include design space exploration capabilities offered to the user. The validity of the presented framework is demonstrated by evaluating and creating CGRA designs of nine applications. Additionally, we provide comparisons of MC-DeF with state-of-the-art related works, and show that MC-DeF offers competitive performance (in terms of internal bandwidth and processing throughput) even compared against much larger designs, and requires fewer physical resources to achieve this level of performance. Finally, MC-DeF is able to better utilize the underlying FPGA fabric and achieves the best efficiency (measured in LUT/GOPs).en
ΤύποςPeer-Reviewed Journal Publicationen
ΤύποςΔημοσίευση σε Περιοδικό με Κριτέςel
Άδεια Χρήσηςhttp://creativecommons.org/licenses/by/4.0/en
Ημερομηνία2023-04-19-
Ημερομηνία Δημοσίευσης2021-
Θεματική ΚατηγορίαComputer systems organization→Data flow architecturesen
Θεματική ΚατηγορίαHardware→Reconfigurable logic and FPGAsen
Θεματική ΚατηγορίαCGRAen
Θεματική ΚατηγορίαCGRA frameworken
Θεματική ΚατηγορίαReconfigurable computingen
Θεματική ΚατηγορίαFPGAen
Βιβλιογραφική ΑναφοράG. Charitopoulos, D. N. Pnevmatikatos and G. Gaydadjiev, “MC-DeF: creating customized CGRAs for dataflow applications,” ACM Trans. Archit. Code Optim., vol. 18, no. 3, Sept. 2021, doi: 10.1145/3447970.en

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