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Συμπίεση βαρών αναδρομικού νευρωνικού δικτύου για την επιτάχυνση αναγνώρισης ωωνής σε αναδιατασσόμενη λογική (FPGA)

Poupakis Alexandros

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Over the last decades, advances in machine learning and neural networks have been unprecedented, with ever more sophisticated models trickling down the mainstream and forming the backbone of products and services we use every day. While cutting edge research in this field has expanded the realm of what is feasible, the learning superiority of deep neural networks is largely attributed to their size. Hardware acceleration of deep learning inference is necessary, for such models to be practically deployable. However, as model size increases rapidly, the available memory bandwidth on massively parallel computing platforms such as FPGAs is outpaced, constituting a bottleneck for scalability. This study addresses the problem of compressing deep neural network weights for inference acceleration on FPGAs. The DeepSpeech2 model for Speech Recognition is trained and used as a case study for weight pruning and quantization. The pièce de résistance of this thesis is the development of a novel compression method suitable for quantized weights, which is tested on the sparse matrices of DeepSpeech2. This method generates a tree of overlapping symbol sequences and uses it to encode the data with mathematically decodable, variable length codes. Importantly, our compression method inherently allows one to coarsely select the decompression throughput. Lastly, the decompressor's architecture is designed and a general model for its resource cost in UltraScale FPGAs is created. When compared against various LZ77-based decompressors in literature, our decompressor consumes more than an order of magnitude fewer logic resources, while being capable of the same or higher throughput.

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