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Ιδρυματικό Αποθετήριο [SANDBOX]
Πολυτεχνείο Κρήτης
Πολυτεχνείο Κρήτης
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| URI: | http://purl.tuc.gr/dl/dias/A0E1733B-54E0-439C-919F-13A335E352C2 | ||
| Έτος | 2019 | ||
| Τύπος | Κεφάλαιο σε Βιβλίο | ||
| Άδεια Χρήσης |
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| Βιβλιογραφική Αναφορά | A.D. Ioannou, P. Malakonakis, K. Georgopoulos, I. Papaefstathiou, A. Dollas and I. Mavroidis, "Optimized FPGA implementation of a compute-intensive oil reservoir simulation algorithm," in Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2019, vol. 11733, Lecture Notes in Computer Science, D. Pnevmatikatos, M. Pelcat, M. Jung, Eds., Cham, Switzerland: Springer Nature, 2019, pp. 442-454. doi: 10.1007/978-3-030-27562-4_32 https://doi.org/10.1007/978-3-030-27562-4_32 | ||
| Εμφανίζεται στις Συλλογές |
Modern-day High Performance Computing (HPC) trends are shifting towards exascale performance figures in order to satisfy the needs of many compute-intensive and power-hungry applications. Hence, the European-funded ECOSCALE project introduces a highly innovative architecture, which spreads the workload among a number of independent and concurrently-operating conventional (CPU) as well as reconfigurable (FPGA) processing elements that execute OpenCL cores whilst significantly minimizing the need for data transfers. The accelerator cores implemented on the ECOSCALE platform correspond to the project use cases and have been the source of a meticulous exploration process for optimal performance results such as execution time. This paper focuses on performance and power optimizations of the Michelsen algorithm. This algorithm is an efficient calculator of the Rachford-Rice equation, which is extensively used in the field of oil Reservoir Simulation (RS). The algorithm was first optimized manually through Vivado HLS and, subsequently, using a Design Space Exploration (DSE) tool we developed in [1]. Here we present up-to-date optimization results based on the latest FPGA ECOSCALE platform in order to reveal bottlenecks, saturation points and design alternatives. The measurements are performed on real data and the evaluation results register significant gains in calculation times over conventional CPU platforms; an achievement that carries added value considering the significantly reduced power consumption costs commonly associated with reconfigurable hardware.
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