![Institutional Repository [SANDBOX]](images/dias.logo.png "Institutional Repository [SANDBOX]"){kind=logo}
Institutional Repository [SANDBOX]
Technical University of Crete
Technical University of Crete
EN
|
EL
| URI | http://purl.tuc.gr/dl/dias/D7AA08D3-1073-4395-B202-EA4ECB7A1235 | - |
| Identifier | https://doi.org/10.1109/JEDS.2019.2944817 | - |
| Identifier | https://ieeexplore.ieee.org/document/8854243 | - |
| Language | en | - |
| Extent | 9 pages | en |
| Title | CJM: a compact model for double-gate junction FETs | en |
| Creator | Makris Nikolaos | en |
| Creator | Μακρης Νικολαος | el |
| Creator | Bucher Matthias | en |
| Creator | Bucher Matthias | el |
| Creator | Jazaeri, Farzan 1984- | en |
| Creator | Sallese, Jean-Michel 1964- | en |
| Publisher | Institute of Electrical and Electronics Engineers | en |
| Content Summary | The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of device fabrication but also its principle of operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Furthermore, co-integration of JFET with CMOS technology is attractive. Physics-based compact models for JFETs are however scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, transconductances and transcapacitances of symmetric DG JFETs, covering all regions of device operation, continuously from subthreshold to linear and saturation operation. This charge-based JFET model (called CJM) constitutes the basis of a full compact model of the DG JFET for analog, RF, and digital circuit simulation. | en |
| Type of Item | Peer-Reviewed Journal Publication | en |
| Type of Item | Δημοσίευση σε Περιοδικό με Κριτές | el |
| License | http://creativecommons.org/licenses/by/4.0/ | en |
| Date of Item | 2020-10-29 | - |
| Date of Publication | 2019 | - |
| Subject | Charge-based model | en |
| Subject | Circuit simulation | en |
| Subject | CJM model | en |
| Subject | Compact model | en |
| Subject | Depletion mode | en |
| Subject | Double gate | en |
| Subject | High frequency | en |
| Subject | JFET | en |
| Subject | Junction field effect transistor | en |
| Subject | Low noise | en |
| Subject | Verilog-A | en |
| Bibliographic Citation | N. Makris, M. Bucher, F. Jazaeri and J.-M. Sallese, "CJM: a compact model for double-gate junction FETs," IEEE J. Electron Devices Soc., vol. 7, pp. 1191-1199, Oct. 2019. doi: 10.1109/JEDS.2019.2944817 | en |
Copyright © DIAS 2013
