Το έργο με τίτλο Compact modeling of SIC and gan junction FETS at high temperature από τον/τους δημιουργό/ούς Makris Nikolaos, Zekentes, Konstantinos, Bucher Matthias διατίθεται με την άδεια Creative Commons Αναφορά Δημιουργού 4.0 Διεθνές
Βιβλιογραφική Αναφορά
N. Makris, K. Zekentes and M. Bucher, “Compact modeling of SiC and GaN junction FETs at high temperature,” Mater. Sci. Forum, vol. 963, pp. 683–687, Jul. 2019. https://doi.org/10.4028/www.scientific.net/msf.963.683
https://doi.org/10.4028/www.scientific.net/MSF.963.683
High temperatures and other harsh environments are domains of predilection for Junction FETs, particularly when wide band-gap semiconductors such as SiC or GaN are used. The present work describes the new compact model of double-gate (DG) JFETs which is compared to TCAD simulations of SiC and GaN JFETs over a wide temperature range up to 500ºC. The compact model is shown to be predictive of device behavior, for static (current-voltage) as well as dynamic (capacitance-voltage) behavior of long-channel DG JFETs.