URI | http://purl.tuc.gr/dl/dias/031B8C04-E832-4A91-A846-FCF577B29607 | - |
Identifier | https://doi.org/10.23919/MIXDES.2019.8787098 | - |
Identifier | https://ieeexplore.ieee.org/abstract/document/8787098 | - |
Language | en | - |
Extent | 4 pages | en |
Title | Forward and reverse operation of enclosed-gate MOSFETs and sensitivity to high total ionizing dose | en |
Creator | Nikolaou Aristeidis | en |
Creator | Νικολαου Αριστειδης | el |
Creator | Chevas Loukas | en |
Creator | Χεβας Λουκας | el |
Creator | Papadopoulou Alexia | en |
Creator | Παπαδοπουλου Αλεξια | el |
Creator | Makris Nikolaos | en |
Creator | Μακρης Νικολαος | el |
Creator | Bucher Matthias | en |
Creator | Bucher Matthias | el |
Creator | Borghello Giulio | en |
Creator | Faccio Federico | en |
Publisher | Institute of Electrical and Electronics Engineers | en |
Content Summary | Frond-end electronics at the High Luminosity-Large Hadron Collider (HL-LHC) at CERN, will be exposed to ten-fold radiation doses. The use of enclosed gate (EG) MOSFETs of 65 nm Bulk CMOS process, is considered to be a viable solution in order to suppress performance degradation effects that occur after high TID exposure. The present paper presents a detailed analysis of the functionality of EG MOSFETs operating under high TID, taking into accountspecific layout characteristics. | en |
Type of Item | Πλήρης Δημοσίευση σε Συνέδριο | el |
Type of Item | Conference Full Paper | en |
License | http://creativecommons.org/licenses/by/4.0/ | en |
Date of Item | 2020-06-05 | - |
Date of Publication | 2019 | - |
Subject | Enclosed layout | en |
Subject | High energy physics | en |
Subject | High-Luminosity Large Hadron Collider | en |
Subject | MOSFETs | en |
Subject | Radiation hardness | en |
Subject | Total ionizing dose | en |
Bibliographic Citation | A. Nikolaou, L. Chevas, A. Papadopoulou, N. Makris, M. Bucher, G. Borghello and F. Faccio, "Forward and reverse operation of enclosed-gate MOSFETs and sensitivity to high total ionizing dose," in 26th International Conference "Mixed Design of Integrated Circuits and Systems", 2019, pp. 306-309. doi: 10.23919/MIXDES.2019.8787098 | en |