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FOSS EKV2.6 Verilog-A compact MOSFET model

Grabiński, Władysław, Pavanello Marcelo Antonio, de Souza Michelly A.S., Tomaszewski Daniel, Malesinska Jola, Guszko Grzegorz, Bucher Matthias, Makris Nikolaos, Nikolaou Aristeidis, Abo-Elhadid Ahmed, Mierzwinski Marek, Lemaitre Laurent, Brinson Mike E., Lallement Christophe, Sallese, Jean-Michel 1964-, Yoshitomi Sadayuki, Malisse Paul, Oguey Henri J., Cserveny Stefan, Enz Christian C., Krummenacher François

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URI: http://purl.tuc.gr/dl/dias/88F6A8F0-4CA8-4C89-A318-C13FCACA8B50
Έτος 2019
Τύπος Πλήρης Δημοσίευση σε Συνέδριο
Άδεια Χρήσης
Λεπτομέρειες
Βιβλιογραφική Αναφορά W. Grabinski, M. Pavanello, M. De Souza, D. Tomaszewski, J. Malesinska, G. Guszko, M. Bucher, N. Makris, A. Nikolaou, A. Abo-Elhadid, M. Mierzwinski, L. Lemaitre, M. Brinson, C. Lallement, J.-M. Sallese, S. Yoshitomi, P. Malisse, H. Oguey, S. Cserveny, C. Enz and F. Krummenacher, "FOSS EKV2.6 Verilog-A compact MOSFET model," in 49th European Solid-State Device Research Conference, 2019, pp. 190-193. doi: 10.1109/ESSDERC.2019.8901822 https://doi.org/10.1109/ESSDERC.2019.8901822
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Περίληψη

The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice.

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