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An FPGA-based architecture to simulate cellular automata with large neighborhoods in real time

Kyparissas Nikolaos, Dollas Apostolos

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URIhttp://purl.tuc.gr/dl/dias/6E4A6214-112B-4C86-864B-C64564839E78-
Identifierhttps://doi.org/10.1109/FPL.2019.00024-
Identifierhttps://ieeexplore.ieee.org/document/8892035-
Languageen-
Extent5 pagesen
TitleAn FPGA-based architecture to simulate cellular automata with large neighborhoods in real timeen
CreatorKyparissas Nikolaosen
CreatorΚυπαρισσας Νικολαοςel
CreatorDollas Apostolosen
CreatorΔολλας Αποστολοςel
PublisherInstitute of Electrical and Electronics Engineersen
Content SummaryIn this paper we present a reconfigurable logic-based parallel architecture for the computation of 29X29 large-neighborhood cellular automata at 60 frames-per-second (FPS) real time update rate, using a small FPGA. The computation for each one of the n^2 elements of a two-dimensional input is O(κ2), where k is the size of the neighborhood in each dimension. All buffering and computation is performed internally in the FPGA. In terms of performance results, our architecture outperforms a general-purpose CPU running highly optimized software programmed in C by up to 51X; in neighborhoods up to 11X11 in which there are published results from GPUs our architecture has similar performance to GPUs at one-tenth the energy requirements, however, our architecture has the same performance for 29X29 neighborhoods whereas GPU performance drops as neighborhood grows. We expect this work to provide enabling new tools for the use of cellular automata models in the physical sciences.en
Type of ItemΠλήρης Δημοσίευση σε Συνέδριοel
Type of ItemConference Full Paperen
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2020-04-23-
Date of Publication2019-
SubjectCellular Automataen
SubjectFPGAen
SubjectLarge Neighborhooden
SubjectReal timeen
Bibliographic CitationN. Kyparissas and A. Dollas, "An FPGA-based architecture to simulate cellular automata with large neighborhoods in real time," in 29th International Conference on Field-Programmable Logic and Applications, 2019, pp. 95-99. doi: 10.1109/FPL.2019.00024en

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