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Full system architectural simulation on the HARP integrated CPU-FPGA platform

Kyriakidis Konstantinos

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Summary

Simulation is vital when developing novel software or hardware systems. Cycle accurate architectural simulators are extremely important tools for verifying experimental hardware platforms, system profiling, and advanced software development. Their main disadvantage is limited throughput when simulating large systems with multiple processing units and peripherals.This Master’s thesis describes the development process of a series of HW components for Intel’s HARP CPU-FPGA hybrid platform, that will be used to synthesize a Trace-Driven FPGAAccelerated Full-System Architectural Simulator. Essential development steps and protocols, that are required to incorporate accelerators on the HARP platform, are also highlighted. The developedmodules, facilitate high-performance HW components that can accurately and efficiently simulate a highly configurable L1 Cache and 3 highly configurable Branch Predictor HW structures.Optimal performance for the proposed HW simulator can be achieved when executed in coordination with a fast functional simulator running on SW. A state of the art API exports trace-data from the functional simulation at run time, in order to load the HW modules. Using these data, the HW modules can accurately and efficiently execute architectural simulation. Apart from simulation results and timing statistics, the models can generate the system’s state at different timestamps, depending on the executed traces. These architectural checkpoints can later be used to either validate the functionality of the components, determine the overall system’s behavior using the sampling technique, execute new architectural simulations, or to warm-up other full system simulations.

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