Institutional Repository [SANDBOX]
Technical University of Crete
EN  |  EL

Search

Browse

My Space

Modeling of high total ionizing dose (TID) effects for enclosed layout transistors in 65 nm bulk CMOS

Nikolaou Aristeidis, Bucher Matthias, Makris Nikolaos, Papadopoulou Alexia, Chevas Loukas, Borghello Jiulio, Koch Henri D., Faccio Federico

Simple record


URIhttp://purl.tuc.gr/dl/dias/8300B063-A1AA-4DBB-BD64-AFD31642A8FC-
Identifierhttps://doi.org/10.1109/SMICND.2018.8539806-
Identifierhttps://ieeexplore.ieee.org/document/8539806-
Languageen-
Extent4 pagesen
TitleModeling of high total ionizing dose (TID) effects for enclosed layout transistors in 65 nm bulk CMOSen
CreatorNikolaou Aristeidisen
CreatorΝικολαου Αριστειδηςel
CreatorBucher Matthiasen
CreatorBucher Matthiasel
CreatorMakris Nikolaosen
CreatorΜακρης Νικολαοςel
CreatorPapadopoulou Alexiaen
CreatorΠαπαδοπουλου Αλεξιαel
CreatorChevas Loukasen
CreatorΧεβας Λουκαςel
CreatorBorghello Jiulioen
CreatorKoch Henri D.en
CreatorFaccio Federicoen
PublisherInstitute of Electrical and Electronics Engineersen
Content SummaryHigh doses of ionizing radiation drastically impair the electrical performance of CMOS technology. Enclosed gate layout remains an effective means to reduce this impact. Nevertheless, high total ionizing dose (TID) effects remain strong. The paper presents an effective approach to analytically model high TID effects in both NMOS and PMOS transistors with enclosed-gate layout in 65 nm commercial CMOS.en
Type of ItemΠλήρης Δημοσίευση σε Συνέδριοel
Type of ItemConference Full Paperen
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2019-05-24-
Date of Publication2018-
SubjectCompact modelingen
SubjectEKV modelen
SubjectEnclosed gate MOSFETsen
SubjectHigh energy physicsen
SubjectHigh total ionizing doseen
SubjectRadiationen
SubjectSpace applicationsen
Bibliographic CitationA. Nikolaou, M. Bucher, N. Makris, A. Papadopoulou, L. Chevas, G. Borghello, H. D. Koch and F. Faccio, "Modeling of high total ionizing dose (TID) effects for enclosed layout transistors in 65 nm bulk CMOS," in 41st International Semiconductor Conference, 2018, pp. 133-136. doi: 10.1109/SMICND.2018.8539806en

Services

Statistics