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Modeling of high total ionizing dose (TID) effects for enclosed layout transistors in 65 nm bulk CMOS

Nikolaou Aristeidis, Bucher Matthias, Makris Nikolaos, Papadopoulou Alexia, Chevas Loukas, Borghello Jiulio, Koch Henri D., Faccio Federico

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URI: http://purl.tuc.gr/dl/dias/8300B063-A1AA-4DBB-BD64-AFD31642A8FC
Year 2018
Type of Item Conference Full Paper
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Bibliographic Citation A. Nikolaou, M. Bucher, N. Makris, A. Papadopoulou, L. Chevas, G. Borghello, H. D. Koch and F. Faccio, "Modeling of high total ionizing dose (TID) effects for enclosed layout transistors in 65 nm bulk CMOS," in 41st International Semiconductor Conference, 2018, pp. 133-136. doi: 10.1109/SMICND.2018.8539806 https://doi.org/10.1109/SMICND.2018.8539806
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Conference Publications in Community School of Electrical and Computer Engineering

Summary

High doses of ionizing radiation drastically impair the electrical performance of CMOS technology. Enclosed gate layout remains an effective means to reduce this impact. Nevertheless, high total ionizing dose (TID) effects remain strong. The paper presents an effective approach to analytically model high TID effects in both NMOS and PMOS transistors with enclosed-gate layout in 65 nm commercial CMOS.

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