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Electrical characterization and compact modeling of power D-MOSFETs

Iosifidis Michail-Ilias

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Summary

The purpose of this diploma thesis is to investigate the electrical behavior of two kinds of modern power transistors, namely Lateral (LDMOS) and Vertical (VDMOS) devices. Both n-type and p-type transistors have been characterized experimentally by both static and dynamic techniques. The measurement setups are discussed along with the equipment used to conduct those measurements. Different transistor geometries are investigated where available. Subsequently, parameter extraction techniques are employed, and the statistics of parameter spread is established. For the VDMOS devices in particular, a modelling approach will be followed, with the measurements being the basis for parameter extraction for the EPFL-HV compact model.This thesis is organized as follows: Chapter 1 is a brief introduction about the importance of D-MOS technology and the model that will be used to simulate their operation, in Chapter 2 the structure and operation of bulk-MOS and the two types of DMOS transistor is described and in Chapter 3 a description of the EPFL-HV MOSFET model is given along with an explanation of the phenomena it can simulate. Chapters 4 and 5, are dedicated to the experimental measurements of two device families, with 4 devices being analyzed three lateral and one vertical. In Chapter 5 the parameter extraction methodology for the EPFL-HV is also described and demonstrated. Finally, Chapter 6 contains the conclusion of this thesis with the experimental deductions and proposals for possible future work.

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