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Implementation of an ARM processor with SIMD extensions using the Bluespec Hardware Description Language

Makrygiannis Konstantinos

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URIhttp://purl.tuc.gr/dl/dias/95931972-5301-4118-AD6D-D9AD1015F29C-
Identifierhttps://doi.org/10.26233/heallink.tuc.75213-
Languageen-
Extent78 pagesen
Extent3,76 megabytesen
TitleImplementation of an ARM processor with SIMD extensions using the Bluespec Hardware Description Languageen
TitleΥλοποίηση επεξεργαστή ARM με επέκταση εντολών SIMD με χρήση Γλώσσας Περιγραφής Υλικού Bluespec el
CreatorMakrygiannis Konstantinosen
CreatorΜακρυγιαννης Κωνσταντινοςel
Contributor [Thesis Supervisor]Pnevmatikatos Dionysiosen
Contributor [Thesis Supervisor]Πνευματικατος Διονυσιοςel
Contributor [Committee Member]Dollas Apostolosen
Contributor [Committee Member]Δολλας Αποστολοςel
Contributor [Committee Member]Theodoropoulos Dimitriosen
Contributor [Committee Member]Θεοδωροπουλος Δημητριοςel
PublisherΠολυτεχνείο Κρήτηςel
PublisherTechnical University of Creteen
Academic UnitTechnical University of Crete::School of Electrical and Computer Engineeringen
Academic UnitΠολυτεχνείο Κρήτης::Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστώνel
Content SummaryThe goal of this thesis was to implement an ARM processor with Single Instruction Multiple Data (SIMD) extensions using the Bluespec System Verilog (BSV) as a Hardware Description Language (HDL). BSV has a fundamentally different approach to hardware design, comparing to other HDLs. It is based on circuit generation - rather than merely circuit description - and on atomic transactional rules instead of a globally synchronous view of the world. BSV language is considered a high-level functional HDL, which was essentially Haskell - extended to handle chip design and electronic design automation in general. BSV is partially evaluated (to convert the Haskell parts) and compiled to the Term Rewriting System (TRS). Our scalar processor supports a 3-stage pipeline (Fetch – Decode – Execute), belongs to the ARM7 family and uses a 32-bit architecture, which is based on ARMv4 instruction set. The SIMD unit works as an extension to the scalar part and is based on a modification of ARM NEON technology. The scalar part of the processor supports Data processing, Multiply, Long Multiply, Load/Store – Byte/Word and Branch instructions of the ARM Instruction Set Format, while the vector part supports Vector Data Processing, Vector Multiply and Vector Load/Store instructions.en
Type of ItemΔιπλωματική Εργασίαel
Type of ItemDiploma Worken
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2018-05-17-
Date of Publication2018-
SubjectBluespecen
SubjectVector processingen
SubjectARMen
Bibliographic CitationKonstantinos Makrygiannis, "Implementation of an ARM processor with SIMD extensions using the Bluespec Hardware Description Language", Diploma Work, School of Electrical and Computer Engineering, Technical University of Crete, Chania, Greece, 2018en
Bibliographic CitationΚωνσταντίνος Μακρυγιάννης, "Υλοποίηση επεξεργαστή ARM με επέκταση εντολών SIMD με χρήση Γλώσσας Περιγραφής Υλικού Bluespec ", Διπλωματική Εργασία, Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών, Πολυτεχνείο Κρήτης, Χανιά, Ελλάς, 2018el

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