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Versatile deployment of FPGA accelerators in disaggregated data centers: a bioinformatics case study

Alachiotis Nikolaos, Theodoropoulos Dimitrios, Pnevmatikatos Dionysios

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Summary

Important design considerations for the cost-effective employment of hardware accelerators in next-generation data centers involve a) the type of candidate applications that a proposed solution can accelerate (generality), and b) the required development effort to successfully deploy the available accelerators for a given application (adoption overhead). To address the problem of generality, we present a versatile and dynamically reconfigurable hardware architecture that exhibits several accelerator slots and programmable interconnect to create application-specific accelerator datapaths. The proposed architecture fits in the model of disaggregated data centers, where compute, memory, and accelerators are broadly regarded as large pools of resources, and subsets of these resource pools are dynamically allocated on an as-needed basis to cooperatively boost performance of a broad range of applications. Initial results for a bioinformatics application that we employ as a case study and deals with the detection of positive selection in large-scale genomic datasets reveal a speedup of up to 6.4X when custom hardware accelerators are mapped to the proposed versatile accelerator architecture and compared with a parallel and highly optimized software implementation executed on a multi-core processor.

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