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A generic high throughput architecture for stream processing

Rousopoulos Christos, Karandeinos Ektor, Chrysos Grigorios, Dollas Apostolos, Pnevmatikatos Dionysios

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URIhttp://purl.tuc.gr/dl/dias/CB1579C1-ADC3-483D-85A1-52010D9CE731-
Identifierhttp://ieeexplore.ieee.org/document/8056796/-
Identifierhttps://doi.org/10.23919/FPL.2017.8056796-
Languageen-
TitleA generic high throughput architecture for stream processingen
CreatorRousopoulos Christosen
CreatorΡουσοπουλος Χρηστοςel
CreatorKarandeinos Ektoren
CreatorΚαρανδεινος Εκτωρel
CreatorChrysos Grigoriosen
CreatorΧρυσος Γρηγοριοςel
CreatorDollas Apostolosen
CreatorΔολλας Αποστολοςel
CreatorPnevmatikatos Dionysiosen
CreatorΠνευματικατος Διονυσιοςel
PublisherInstitute of Electrical and Electronics Engineersen
Content SummaryStream join is a fundamental and computationally expensive data mining operation for relating information from different data streams. This paper presents two FPGA-based architectures that accelerate stream join processing. The proposed hardware-based systems were implemented on a multi-FPGA hybrid system with high memory bandwidth. The experimental evaluation shows that our proposed systems can outperform a software-based solution that runs on a high-end, 48-core multiprocessor platform by at least one order of magnitude. In addition, the proposed solutions outperform any other previously proposed hardware-based or software-based solutions for stream join processing. Finally, our proposed hardware-based architectures can be used as generic templates to map stream processing algorithms on reconfigurable logic, taking into consideration real-world challenges and restrictions.en
Type of ItemΠλήρης Δημοσίευση σε Συνέδριοel
Type of ItemConference Full Paperen
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2018-03-22-
Date of Publication2017-
SubjectStream processingen
Bibliographic CitationC. Rousopoulos, E. Karandeinos, G. Chrysos, A. Dollas and D.N. Pnevmatikatos, "A generic high throughput architecture for stream processing," in 27th International Conference on Field Programmable Logic and Applications, 2017. doi:10.23919/FPL.2017.8056796el

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