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Tool for optimized design of integrated RF CMOS low noise amplifiers

Papadimitriou Aggelos

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Summary

The demand for larger bandwidth in wireless communications, motivates the RF circuit designers to advance to higher frequencies in order to serve the rapidly growing market. CMOS technology has dominated in the design of radio frequency and analog integrated circuits. Using devices in the nanometer regime, provides the possibility for greater operation frequencies and ultimately faster data rates. Additionally, RF circuit design is increasingly taking advantage of the aggressive scaling of submicrometer CMOS technologies that make possible the integration of complete tele-communication systems in a single chip (SoC). Low noise amplifiers (LNA) are one of the most important blocks of any telecommunication system. Their importance lies on the fact that they impact the noise performance more than any of the other blocks in the receiver chain. The main purpose of the low noise amplifier is to increase the power of the attenuated input signal, while at the same time minimizing the noise added to the chain by the circuit itself. In the RF design procedure, a designer faces the problem of trade-offs in quantities like consumption, gain, linearity etc. The purpose of this thesis is the introduction of a theoretical model that defines the optimum operation of a LNA (figure-of-merit) and afterwards the introduction of a design methodology that approaches the theoretical response. The thesis also proposes the integration of a genetic algorithm in the design sequence, that finds actual optimum solutions using the procedures of natural selection, reproduction and mutation. Finally, the efficiency of the equation model and genetic algorithm combination is showcased with the design of an optimum 5 GHz common source LNA. The optimal LNA design is obtained in the region of moderate inversion, according to both the analytical model and the optimization procedure. Furthermore, the other LNA topologies such as cascode LNA and common gate LNA are also evaluated. This work provides valuable insight into the design trade-offs of the different LNA topologies.

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