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Institutional Repository [SANDBOX]
Technical University of Crete
Technical University of Crete
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| URI: | http://purl.tuc.gr/dl/dias/C8896114-E412-4925-8A58-D15387350A77 | ||
| Year | 1994 | ||
| Type of Item | Conference Publication | ||
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| Bibliographic Citation | J. D. Sterling Babcock and A. Dollas, "Extended VHDL for the rapid prototyping of systems with synthesizable and nonsynthesizable subsystems," in Fifth International Workshop on Rapid System Prototyping, 1994, pp. 146-152. doi: 10.1109/IWRSP.1994.315900 https://doi.org/10.1109/IWRSP.1994.315900 | ||
| Appears in Collections |
System design is typically done in VHDL to facilitate top-down design and to enable the mapping of a design to many implementations. Reusability of subsystems to date has largely been performed with libraries of synthesizable VHDL subsystems. This paper presents recommended extensions to VHDL to allow the VHDL designer to interact with nonsynthesizable subsystems while still designing in VHDL. The extended VHDL code is passed through a precompiler that outputs two standard VHDL files: a simulatable VHDL model of the system, and a synthesizable model of the design where subsystems are replaced by signals to the external hardware.
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