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A case study of system synthesis with non-synthesizable components using extended VHDL

Sterling Babcock J. D. , Dollas Apostolos

Πλήρης Εγγραφή


URI: http://purl.tuc.gr/dl/dias/DCCAB709-B271-4395-9832-0B62E9A963DA
Έτος 1995
Τύπος Πλήρης Δημοσίευση σε Συνέδριο
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Βιβλιογραφική Αναφορά J. D. Sterling Babcock and A. Dollas, "A case study of system synthesis with non-synthesizable components using extended VHDL," in Sixth IEEE International Workshop on Rapid System Prototyping, 1995, pp. 168-173. doi:10.1109/IWRSP.1995.518587 https://doi.org/10.1109/IWRSP.1995.518587
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Περίληψη

Extensions to VHDL have been defined in order to produce a compiler that allows for system design with synthesizable and non-synthesizable multi-chip subsystems. The compiler has been completed and this paper presents a case study that has been made to evaluate the merits and limitations of this approach. Finally, a brief discussion is made of the error generation. Capability that results from the use of formal methods in the definition of the VHDL language extensions.

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