Ιδρυματικό Αποθετήριο [SANDBOX]
Πολυτεχνείο Κρήτης
EN  |  EL

Αναζήτηση

Πλοήγηση

Ο Χώρος μου

Accelerating emulation and providing full chip observability and controllability

Papaefstathiou Ioannis, Mavroidis I., Mavroidis D.

Πλήρης Εγγραφή


URI: http://purl.tuc.gr/dl/dias/43BE691B-1554-480A-AD49-62BB1A7E7A00
Έτος 2009
Τύπος Δημοσίευση σε Περιοδικό με Κριτές
Άδεια Χρήσης
Λεπτομέρειες
Βιβλιογραφική Αναφορά I. Mavroidis, D. Mavroidis, I. Papaefstathiou, "Accelerating Emulation and Providing Full Chip Observability and Controllability," IEEE Design and Test, vol. 26, no. 6, pp. 84-94, Nov./Dec. 2009. doi: 10.1109/MDT.2009.136 https://doi.org/10.1109/MDT.2009.136
Εμφανίζεται στις Συλλογές

Περίληψη

Performing hardware emulation on FPGAs is a significantly faster and more accurate approach for the verification of complex designs than software simulation. Therefore, hardware Simulation Accelerator and Emulator co-processor units are used to offload calculation-intensive tasks from the software simulator. However, the communication overhead between the software simulator and the hardware emulator is becoming a new critical bottleneck. Moreover, in a hardware emulation environment it is impossible to bring outside of the chip a large number of internal signals for verification purposes. Therefore, on-chip observability has become a significant issue. In our work we tackle both aforementioned problems. First, we deploy a novel emulation framework that automatically transforms into synthesizable code certain HDL parts of the testbench, in order to offload them from the software simulator and, more importantly, minimize the aforementioned communication overhead. Next, we extend this architecture by adding multiple fast scan-chain paths in the design in order to provide full circuit observability and controllability on the fly. In this paper, we briefly describe our approach for reducing the communication overhead problem, and present, for the first time, our complete innovative system which offers extensive observability and controllability in complex Design Under Tests (DUTs).

Υπηρεσίες

Στατιστικά