Institutional Repository [SANDBOX]
Technical University of Crete
EN  |  EL

Search

Browse

My Space

An innovative scheduling scheme for high-speed network processors

Papaefstathiou Ioannis, Kornaros Georgios, Leligou H., Orphanoudakis T., Zervos N.

Simple record


URIhttp://purl.tuc.gr/dl/dias/8267D48E-712D-4156-B197-FDD67C1CE702-
Identifierhttps://doi.org/10.1109/ISCAS.2003.1205899-
Languageen-
TitleAn innovative scheduling scheme for high-speed network processorsen
CreatorPapaefstathiou Ioannisen
CreatorΠαπαευσταθιου Ιωαννηςel
CreatorKornaros Georgiosen
CreatorΚορναρος Γεωργιοςel
CreatorLeligou H.en
CreatorOrphanoudakis T.en
CreatorZervos N.en
PublisherInstitute of Electrical and Electronics Engineersen
Content SummaryIn this paper, we describe the architecture of the scheduling components integrated in a novel programmable processor architecture. The paper explores the requirements for scheduling in the environment of a network processor, designed for efficient protocol processing in high-speed networking. We focus on the implementation of services with weighted priorities and shaping of traffic on the transmission path as a means to support QoS for real time applications. Taking into account that one of the main problems when designing hardware devices for network processing is the relatively low throughput and capacity of the memories (mainly off-chip) we describe design alternatives and analyze the performance vs. cost trade-offs. The architecture of a novel processor architecture developed by the Protocol Processor Project (PRO3) is described and is used as reference to explore the intricacies of the scheduler components and identify parameters that affect the components design and performance.en
Type of ItemΠλήρης Δημοσίευση σε Συνέδριοel
Type of ItemConference Full Paperen
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2015-11-16-
Date of Publication2003-
Bibliographic CitationI. Papaefstathiou, H. Leligou, T. Orphanoudakis, G. Kornaros, N. Zervos, G. Konstantoulakis, "An innovative scheduling scheme for high-speed network processors," in IEEE International Symposium on Circuits and Systems, 2003, pp. II-93 - II-96. doi: 10.1109/ISCAS.2003.1205899en

Services

Statistics