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Ιδρυματικό Αποθετήριο [SANDBOX]
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| URI | http://purl.tuc.gr/dl/dias/8A31BC37-007D-4EA6-BC32-179B23C9F3B8 | - |
| Αναγνωριστικό | https://doi.org/10.1109/FPL.2009.5272287 | - |
| Γλώσσα | en | - |
| Τίτλος | A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems | en |
| Δημιουργός | Papaefstathiou Ioannis | en |
| Δημιουργός | Παπαευσταθιου Ιωαννης | el |
| Δημιουργός | Sotiropoulos I. | en |
| Εκδότης | Institute of Electrical and Electronics Engineers | en |
| Περίληψη | In this paper we present a reconfigurable device which significantly improves the execution time of the most computational intensive functions of three of the most widely used face recognition algorithms; those tasks multiply very large dense matrices. The presented architecture utilizes numerous digital signal processing units (DSPs) organized in a parallel manner within a state-of-the-art FPGA device. In order to accelerate those functions we have implemented a ldquoblockedrdquo matrix multiplication algorithm which multiplies certain sub-matrices of fixed-point 32-bit numbers; the size of the sub-matrices has been selected so as to fully exploit the resources of the underlying reconfigurable device. Our system is up to 550 times faster than a conventional general purpose processor when implementing the most CPU intensive parts of a number of very widely used face identification schemes, whereas it is more than 40 times faster than the similar schemes implemented in reconfigurable devices. Moreover, our system is general enough so as to be efficiently utilized in any application incorporating fixed-point matrix multiplications. | en |
| Τύπος | Πλήρης Δημοσίευση σε Συνέδριο | el |
| Τύπος | Conference Full Paper | en |
| Άδεια Χρήσης | http://creativecommons.org/licenses/by/4.0/ | en |
| Ημερομηνία | 2015-11-15 | - |
| Ημερομηνία Δημοσίευσης | 2009 | - |
| Βιβλιογραφική Αναφορά | I. Papaefstathiou, I. Sotiropoulos, "A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems," in International Conference on Field Programmable Logic and Applications, 2009, pp. 276 - 281. doi: 10.1109/FPL.2009.5272287 | en |
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