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Architecture, design, and experimental evaluation of a lightfield descriptor depth buffer algorithm on reconfigurable Logic and on a GPU

Papaefstathiou Ioannis, Dollas Apostolos, Lakka M., Chrysos Grigorios

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URIhttp://purl.tuc.gr/dl/dias/F78EC01A-27CD-491E-99D6-B8F8AC5D3549-
Identifierhttps://doi.org/10.1109/FCCM.2011.54-
Identifierhttp://ieeexplore.ieee.org/document/5771248/-
Languageen-
Extent8 pagesen
TitleArchitecture, design, and experimental evaluation of a lightfield descriptor depth buffer algorithm on reconfigurable Logic and on a GPUel
CreatorPapaefstathiou Ioannisen
CreatorΠαπαευσταθιου Ιωαννηςel
CreatorDollas Apostolosen
CreatorΔολλας Αποστολοςel
CreatorLakka M.en
CreatorChrysos Grigoriosen
CreatorΧρυσος Γρηγοριοςel
PublisherInstitute of Electrical and Electronics Engineersen
Content SummaryThe Lightfield descriptor method for 3D computer graphics offers the highest quality object retrieval from a database at the expense of higher storage and computational cost vs. other methods. This paper presents two special purpose architectures, based on FPGAs and GPUs, for the depth buffer extraction algorithm which is used by the Light field Descriptor method. The two architectures were fully designed and implemented in hardware on a Virtex 5 FPGA Device and on a GeForce GPU. The FPGA-based design offers a measured average speedup of 50x vs. software. The corresponding GPU results were by comparison less promising, but still better than software solutions. Results reported in this paper are from actual runs on hardware.en
Type of ItemΠλήρης Δημοσίευση σε Συνέδριοel
Type of ItemConference Full Paperen
Licensehttp://creativecommons.org/licenses/by/4.0/en
Date of Item2015-11-15-
Date of Publication2011-
SubjectComputer architectureen
Bibliographic CitationG. Chrysos, I. Papaefstathiou, A. Dollas, M. Lakka, "Architecture, design, and experimental evaluation of a lightfield descriptor depth buffer algorithm on reconfigurable logic and on a GPU," in IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011, pp. 57-64. doi: 10.1109/FCCM.2011.54en

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