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Institutional Repository [SANDBOX]
Technical University of Crete
Technical University of Crete
EN
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EL
| URI | http://purl.tuc.gr/dl/dias/FFD65D39-9A2F-4134-A43E-F7280EE8F36F | - |
| Identifier | http://users.isc.tuc.gr/~kpapadimitriou/publications/2015arc-HWTaskSchedPRfpgas.pdf | - |
| Language | en | - |
| Title | Hardware task scheduling for partially reconfigurable FPGAs | en |
| Creator | Charitopoulos Georgios | en |
| Creator | Χαριτοπουλος Γεωργιος | el |
| Creator | Koidis Iosif | en |
| Creator | Κοϊδης Ιωσηφ | el |
| Creator | Papadimitriou Kyprianos | en |
| Creator | Παπαδημητριου Κυπριανος | el |
| Creator | Pnevmatikatos Dionysios | en |
| Creator | Πνευματικατος Διονυσιος | el |
| Content Summary | Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the functionality of computing systems, swapping in and out HW tasks. To coordinate the on-demand task execution, we propose and implement a run time system manager for scheduling software (SW) tasks on available processor(s) and hardware (HW) tasks on any number of reconfigurable regions of a partially reconfigurable FPGA. Fed with the initial partitioning of the application into tasks, the corresponding task graph, and the available task mappings, the RTSM considers the runtime status of each task and region, e.g. busy, idle, scheduled for reconfiguration/execution etc., to execute tasks. Our RTSM supports task reuse and configuration prefetching to minimize reconfigurations, task movement among regions to efficiently manage the FPGA area, and RR reservation for future reconfiguration and execution. We validate its correctness using our RTSM to execute an image processing application on a ZedBoard platform. We also evaluate its features within a simulation framework, and find that despite the technology limitations, our approach can give promising results in terms of quality of scheduling. | en |
| Type of Item | Πλήρης Δημοσίευση σε Συνέδριο | el |
| Type of Item | Conference Full Paper | en |
| License | http://creativecommons.org/licenses/by/4.0/ | en |
| Date of Item | 2015-11-12 | - |
| Date of Publication | 2015 | - |
| Subject | Automatic computers | en |
| Subject | Automatic data processors | en |
| Subject | Computer hardware | en |
| Subject | Computing machines (Computers) | en |
| Subject | Electronic brains | en |
| Subject | Electronic calculating-machines | en |
| Subject | Electronic computers | en |
| Subject | Hardware, Computer | en |
| Subject | computers | en |
| Subject | automatic computers | en |
| Subject | automatic data processors | en |
| Subject | computer hardware | en |
| Subject | computing machines computers | en |
| Subject | electronic brains | en |
| Subject | electronic calculating machines | en |
| Subject | electronic computers | en |
| Subject | hardware computer | en |
| Bibliographic Citation | G. Charitopoulos, I. Koidis, K. Papadimitriou and D. Pnevmatikatos, "Hardware Task Scheduling for Partially Reconfigurable FPGAs", in HiPEAC Workshop on Reconfigurable Computing (WRC), January 2015. | en |
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