Least-squares iterative solution on a fixed-size VLSI architecture

URI	http://purl.tuc.gr/dl/dias/15FC95C4-8755-4EFC-AEE9-07495E93EEF8	-
Language	en	-
Title	Least-squares iterative solution on a fixed-size VLSI architecture	en
Creator	T. S. Papatheodorou	en
Creator	Papadopoulou Eleni	en
Creator	Παπαδοπουλου Ελενη	el
Publisher	Springer Link	en
Content Summary	The VLSI implementation of the Accelerated Overrelaxation (AOR) method, when used for the accurate computation of the least-squares solutions of overdetermined systems, is the problem addressed here. As the size of this computational task is usually very large, we use space-time domain expansion techniques to partition the computation and map it onto a fixed size VLSI architecture.	en
Type of Item	Peer-Reviewed Journal Publication	en
Type of Item	Δημοσίευση σε Περιοδικό με Κριτές	el
License	http://creativecommons.org/licenses/by/4.0/	en
Date of Item	2015-10-20	-
Date of Publication	2005	-
Bibliographic Citation	Least Squares Iterative Solution on a Fixed Size VLSI Architecture , E.P. Papadopoulou, T.S. Papatheodorou, Springer Verlag Lecture Notes in Computer Science, Vol.297, pp. 914-925. May 2005	en

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